On 10/10/25 4:39 PM, Anna Maniscalco wrote:
> Update last_fence in the vm-bind path instead of kernel managed path.
>
> last_fence is used to wait for work to finish in vm_bind contexts but not
> used for kernel managed contexts.
>
> This fixes a bug where last_fence is not waited on context clos
On 10/8/25 4:05 PM, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg
>
> Describe panel Tearing Effect (TE) GPIO line.
>
> Reviewed-by: Konrad Dybcio
> Signed-off-by: David Heidelberg
> ---
> arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi |
On 9/26/25 3:53 PM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 02:29:55PM +0530, Mani Chandana Ballary Kuntumalla
> wrote:
>> This change enables display1 clock controller.
>>
>> Signed-off-by: Mani Chandana Ballary Kuntumalla
>> ---
>> arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4
he same time.
>
> To prevent this, introduce a mutual exclusion check between USB and DP
> PHY modes.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Xiangxu Yin
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 9/26/25 1:18 PM, Konrad Dybcio wrote:
> On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
>> The Qualcomm SA8775P platform comes with 2 DisplayPort controllers
>> for each mdss. Update controller id for DPTX0 and DPTX1 of mdss1.
>>
>> Signed-off-by: Mani
On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
> The Qualcomm SA8775P platform comes with 2 DisplayPort controllers
> for each mdss. Update controller id for DPTX0 and DPTX1 of mdss1.
>
> Signed-off-by: Mani Chandana Ballary Kuntumalla
> ---
> drivers/gpu/drm/msm/dp/dp_display.c |
On 9/26/25 11:25 AM, Ayushi Makhija wrote:
> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>>> Add device tree nodes for the DSI0 controller with their corresponding
>>> PHY found on Qualcomm QCS8300 SoC.
>>>
>>> Signed-off-by: Ayus
On 9/25/25 11:12 AM, David Heidelberg via B4 Relay wrote:
> This patchset enables display on the OnePlus 6T smartphone.
>
> Minor adjust to the device-tree of OnePlus 6 had to be done
> to properly document reset GPIO used. Also same adjustments
> had been done to the sofef00 panel driver (used by
On 9/25/25 11:12 AM, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg
>
> Document panel Tearing Effect (TE) GPIO line.
"document" is a keyword in DT context, perhaps "describe" is what
you're looking for
with that changed:
Reviewed-by: Konrad Dybcio
Konrad
On 9/25/25 11:12 AM, David Heidelberg via B4 Relay wrote:
> From: Casey Connolly
>
> There are two additional supplies used by the panel, both are GPIO
> controlled and are left enabled by the bootloader for continuous splash.
>
> Previously these were (incorrectly) modelled as pinctrl. Describe
On 9/8/25 10:27 AM, Akhil P Oommen wrote:
> Add the IFPC restore register list and enable IFPC support on Adreno
> X1-85 gpu.
>
> Signed-off-by: Akhil P Oommen
> ---
[...]
> @@ -1432,12 +1495,14 @@ static const struct adreno_info a7xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTI
On 9/9/25 1:16 PM, Dmitry Baryshkov wrote:
> On Tue, Sep 09, 2025 at 09:14:49AM +0200, Neil Armstrong wrote:
>> On 08/09/2025 23:14, Dmitry Baryshkov wrote:
>>> On Mon, Sep 08, 2025 at 03:04:20PM +0200, Neil Armstrong wrote:
The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
On 9/10/25 2:01 PM, Aleksandrs Vinarskis wrote:
> From: Hans de Goede
>
> Add 'name' argument to of_led_get() such that it can lookup LEDs in
> devicetree by either name or index.
>
> And use this modified function to add devicetree support to the generic
> (non devicetree specific) [devm_]led_g
On 8/18/25 9:17 AM, Akhil P Oommen wrote:
> On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote:
>> On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote:
>>> On 8/14/25 6:38 PM, Akhil P Oommen wrote:
>>>> On 8/14/2025 7:56 PM, Neil Armstrong wrote:
>>>
he next block's header.
>
> Fixes: c6ed04f856a4 ("drm/msm/a6xx: A640/A650 GMU firmware path")
> Signed-off-by: Akhil P Oommen
> ---
I'm not sure what memcpy translates into for unaligned addresses,
but I'm going to assume it's handled properly..
Acked-by: Konrad Dybcio
Konrad
On 9/8/25 10:27 AM, Akhil P Oommen wrote:
> There are some special registers which are accessible even when GX power
> domain is collapsed during an IFPC sleep. Accessing these registers
> wakes up GPU from power collapse and allow programming these registers
> without additional handshake with GMU
On 9/12/25 4:15 AM, Xiangxu Yin wrote:
>
> On 9/12/2025 9:24 AM, Dmitry Baryshkov wrote:
>> On Thu, Sep 11, 2025 at 10:55:01PM +0800, Xiangxu Yin wrote:
>>> Introduce QCS615 hardware-specific configuration for DP PHY mode,
>>> including register offsets, initialization tables, voltage swing
>>> an
On 9/9/25 10:39 PM, Hans de Goede wrote:
> Hi,
>
> On 9-Sep-25 6:57 PM, Aleksandrs Vinarskis wrote:
>>
>>
>>
>>
>>
>> On Monday, September 8th, 2025 at 01:18, Aleksandrs Vinarskis
>> wrote:
>>
>>>
>>>
>>> Introduce common generic led consumer binding, where consumer defines
>>> led(s) by phandle
; + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
Akhil mentioned offline that having this clock under the GMU node
is a hw team recommendation that's rather platform-specific
Reviewed-by: Konrad Dybcio
Konrad
On 9/10/25 2:54 PM, Aleksandrs Vinarskis wrote:
>
>
>
>
>
> On Wednesday, September 10th, 2025 at 14:22, Konrad Dybcio
> wrote:
>
>>
>>
>> On 9/10/25 2:01 PM, Aleksandrs Vinarskis wrote:
>>
>>> From: Hans de Goede ha...@kernel.org
gnation.
> Unlike initially proposed trigger-source based approach, this solution
> cannot be easily bypassed from userspace, thus reducing privacy
> concerns.
>
> Signed-off-by: Aleksandrs Vinarskis
> ---
Reviewed-by: Konrad Dybcio
Konrad
urav Kohli
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
you'll probably want to turn the 115 trip point into 'critical'
(which is fine to do in a separate patch)
Konrad
On 9/8/25 9:39 PM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p chipset. Also, add the speedbin
> qfprom node and wire it up with GPU node.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
On 9/8/25 9:33 AM, Hans de Goede wrote:
> Hi,
>
> On 8-Sep-25 09:20, Konrad Dybcio wrote:
>> On 9/8/25 1:18 AM, Aleksandrs Vinarskis wrote:
>>> A number of existing schemas use 'leds' property to provide
>>> phandle-array of LED(s) to the consumer. Addi
On 9/7/25 1:02 AM, Rob Clark wrote:
> On Sat, Sep 6, 2025 at 1:56 PM Akhil P Oommen
> wrote:
>>
>> On 9/3/2025 8:44 PM, Konrad Dybcio wrote:
>>> On 9/3/25 4:00 PM, Dmitry Baryshkov wrote:
>>>> On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio
known low power state which is not
> exposed by the GMU firmware.
>
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 9/8/25 10:26 AM, Akhil P Oommen wrote:
> A7XX_GEN2 generation has additional TCS slots. Poll the respective
> DRV status registers before pm suspend.
>
> Fixes: 1f8c29e80066 ("drm/msm/a6xx: Add A740 support")
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 +
On 9/8/25 1:18 AM, Aleksandrs Vinarskis wrote:
> A number of existing schemas use 'leds' property to provide
> phandle-array of LED(s) to the consumer. Additionally, with the
> upcoming privacy-led support in device-tree, v4l2 subnode could be a
> LED consumer, meaning that all camera sensors shoul
On 9/4/25 9:55 AM, Yongxing Mou wrote:
>
>
> On 9/4/2025 3:22 PM, Yongxing Mou wrote:
>> This series introduces support to enable the Mobile Display Subsystem (MDSS)
>> , Display Processing Unit (DPU), DisplayPort controller for the Qualcomm
>> QCS8300 target. It includes the addition of the hard
On 9/5/25 9:59 AM, Aleksandrs Vinarskis wrote:
> Introduce common generic led consumer binding, where consumer defines
> led(s) by phandle, as opposed to trigger-source binding where the
> trigger source is defined in led itself.
>
> Add already used in some schemas 'leds' parameter which expects
On 9/5/25 9:59 AM, Aleksandrs Vinarskis wrote:
> Leverage newly introduced 'leds' and 'led-names' properties to pass
> indicator's phandle and function to v4l2 subnode. The latter supports
> privacy led since couple of years ago under 'privacy-led' designation.
> Unlike initially proposed trigger-s
ker is happy, I'm generally happy as well
Reviewed-by: Konrad Dybcio
Konrad
On 9/4/25 11:31 AM, Yongxing Mou wrote:
>
>
> On 9/4/2025 4:21 PM, Konrad Dybcio wrote:
>> On 9/4/25 9:55 AM, Yongxing Mou wrote:
>>>
>>>
>>> On 9/4/2025 3:22 PM, Yongxing Mou wrote:
>>>> This series introduces support to enable the Mobile Di
On 9/3/25 3:58 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 03, 2025 at 03:41:45PM +0200, Konrad Dybcio wrote:
>> On 9/3/25 1:58 PM, Dmitry Baryshkov wrote:
>>> From: Jessica Zhang
>>>
>>> Update Qualcomm DT files in order to declare extra stream pixel clocks
>
On 9/3/25 4:00 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote:
>> On 9/3/25 2:39 PM, Dmitry Baryshkov wrote:
>>> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote:
>>>> On 8/21/25 8:55 PM, Akhil P Oommen
On 9/3/25 1:58 PM, Dmitry Baryshkov wrote:
> From: Jessica Zhang
>
> Update Qualcomm DT files in order to declare extra stream pixel clocks
> and extra register resources used on these platforms to support
> DisplayPort MST.
>
> The driver will continue to work with the old DTS files as even aft
On 9/3/25 2:39 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote:
>> On 8/21/25 8:55 PM, Akhil P Oommen wrote:
>>> From: Puranam V G Tejaswi
>>>
>>> Add gpu and gmu nodes for sa8775p chipset. As of now all
>>>
On 8/21/25 8:55 PM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p chipset. As of now all
> SKUs have the same GPU fmax, so there is no requirement of
> speed bin support.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Reviewed
On 8/21/25 8:55 PM, Akhil P Oommen wrote:
> From: Gaurav Kohli
>
> Unlike the CPU, the GPU does not throttle its speed automatically when it
> reaches high temperatures.
>
> Set up GPU cooling by throttling the GPU speed
> when reaching 105°C.
>
> Signed-off-by: Gaurav Kohli
> Signed-off-by: A
On 9/3/25 12:47 PM, Barnabás Czémán wrote:
>
>
> On 3 September 2025 12:42:38 CEST, Konrad Dybcio
> wrote:
>> On 8/31/25 2:29 PM, Barnabás Czémán wrote:
>>> From: Dang Huynh
>>>
>>> Add initial support for MSM8937 SoC.
>>>
>>>
On 8/31/25 2:29 PM, Barnabás Czémán wrote:
> From: Dang Huynh
>
> Add initial support for MSM8937 SoC.
>
> Signed-off-by: Dang Huynh
> Co-developed-by: Barnabás Czémán
> Signed-off-by: Barnabás Czémán
> ---
[...]
> + qfprom: qfprom@a4000 {
> + compatible = "q
On 9/2/25 5:57 PM, Rob Clark wrote:
> On Tue, Sep 2, 2025 at 5:33 AM Konrad Dybcio
> wrote:
>>
>> On 9/2/25 1:50 PM, Akhil P Oommen wrote:
>>> It is not obvious why we can skip error checking of
>>> dev_pm_opp_find_freq_exact() API. Add a comment explainin
On 9/2/25 3:02 PM, Dmitry Baryshkov wrote:
> On Tue, Sep 02, 2025 at 02:30:48PM +0200, Konrad Dybcio wrote:
>> On 9/2/25 1:50 PM, Akhil P Oommen wrote:
>>> During bringup of a new GPU support, it is convenient to have knob to
>>> quickly disable GPU, but keep the dis
On 9/1/25 2:32 PM, Xiangxu Yin wrote:
>
> On 8/28/2025 7:05 PM, Dmitry Baryshkov wrote:
>> On 28/08/2025 07:51, Xiangxu Yin wrote:
>>>
>>> On 8/20/2025 6:18 PM, Dmitry Baryshkov wrote:
On Wed, Aug 20, 2025 at 05:34:43PM +0800, Xiangxu Yin wrote:
> Add DisplayPort controller for Qualcomm S
On 9/2/25 1:50 PM, Akhil P Oommen wrote:
> During bringup of a new GPU support, it is convenient to have knob to
> quickly disable GPU, but keep the display support. This helps to
> fallback to 'kms_swrast' in case of bootup issues due to GPU. Add a
> modparam to support this.
I'm not entirely opp
bably mention that known == we just retrieved it a couple
function calls above, but I suppose the reader can come up with such
conclusions
Reviewed-by: Konrad Dybcio
Konrad
On 9/2/25 1:50 PM, Akhil P Oommen wrote:
> Current parser logic for GMU firmware assumes a dword aligned payload
> size for every block. This is not true for all GMU firmwares. So, fix
> this by using correct 'size' value in the calculation for the offset
> for the next block's header.
Hm, I haven
On 9/2/25 11:00 AM, Neil Armstrong wrote:
> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
> of a combo glue to route either lanes to the 4 shared physical lanes.
>
> The routing of the lanes can be:
> - 2 DP + 2 USB3
> - 4 DP
> - 2 USB3
>
> The layout of the lanes was designed t
On 8/14/25 6:38 PM, Akhil P Oommen wrote:
> On 8/14/2025 7:56 PM, Neil Armstrong wrote:
>> Hi,
>>
>> On 14/08/2025 13:22, Konrad Dybcio wrote:
>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote:
>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote:
>>>>&
On 8/14/25 1:21 PM, Konrad Dybcio wrote:
> On 7/31/25 12:19 PM, Konrad Dybcio wrote:
>> On 7/25/25 10:35 AM, Neil Armstrong wrote:
>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>>> the Frequency and Power Domain level, but by default we l
On 7/31/25 12:19 PM, Konrad Dybcio wrote:
> On 7/25/25 10:35 AM, Neil Armstrong wrote:
>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>> the Frequency and Power Domain level, but by default we leave the
>> OPP core scale the interconnect ddr path.
On 8/14/25 1:19 AM, Amirreza Zarrabi wrote:
>
>
> On 8/14/2025 8:49 AM, Konrad Dybcio wrote:
>> On 8/14/25 12:24 AM, Amirreza Zarrabi wrote:
>>>
>>>
>>> On 8/13/2025 8:00 PM, Konrad Dybcio wrote:
>>>> On 8/13/25 2:35 AM, Amirreza Zarrabi w
On 8/13/25 11:37 PM, Amirreza Zarrabi wrote:
>
>
> On 8/13/2025 7:53 PM, Konrad Dybcio wrote:
>> On 8/13/25 2:35 AM, Amirreza Zarrabi wrote:
>>> Qualcomm TEE (QTEE) hosts Trusted Applications (TAs) and services in
>>> the secure world, accessed via object
On 8/14/25 12:24 AM, Amirreza Zarrabi wrote:
>
>
> On 8/13/2025 8:00 PM, Konrad Dybcio wrote:
>> On 8/13/25 2:35 AM, Amirreza Zarrabi wrote:
>>> Enable userspace to allocate shared memory with QTEE. Since
>>> QTEE handles shared memory as object, a wrapper is imp
On 8/13/25 2:35 AM, Amirreza Zarrabi wrote:
> Anyone with access to contiguous physical memory should be able to
> share memory with QTEE using shm_bridge.
>
> Tested-by: Neil Armstrong
> Tested-by: Harshal Dev
> Signed-off-by: Amirreza Zarrabi
> ---
Hm, I thought the idea for the tzmem alloca
On 8/13/25 2:35 AM, Amirreza Zarrabi wrote:
> Enable userspace to allocate shared memory with QTEE. Since
> QTEE handles shared memory as object, a wrapper is implemented
> to represent tee_shm as an object. The shared memory identifier,
> obtained through TEE_IOC_SHM_ALLOC, is transferred to the d
On 8/13/25 2:35 AM, Amirreza Zarrabi wrote:
> Qualcomm TEE (QTEE) hosts Trusted Applications (TAs) and services in
> the secure world, accessed via objects. A QTEE client can invoke these
> objects to request services. Similarly, QTEE can request services from
> the nonsecure world using objects ex
On 8/9/25 10:36 AM, Dmitry Baryshkov wrote:
> None of MDP5 platforms have a LUT clock on the display-controller, it
8974 and friends seem to bind it to the GDSC
although on msm-3.4:
arch/arm/mach-msm/clock-8974.c
4197:static struct branch_clk mdss_mdp_lut_clk = {
4203: .dbg_name = "mds
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
gned-off-by: Brian Masney
> ---
Reviewed-by: Konrad Dybcio
Konrad
I did a few minor cosmetic cleanups of the code in a
> few cases.
Reviewed-by: Konrad Dybcio
Konrad
On 8/8/25 7:22 PM, Akhil P Oommen wrote:
> On 8/7/2025 7:21 PM, Konrad Dybcio wrote:
>> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>>> Since the PDC resides out of the GPU subsystem and cannot be reset in
>>> case it enters bad state, utmost care must be taken to tri
eep/wake sequences appropriately.
>
> Signed-off-by: Akhil P Oommen
> ---
FWIW some time ago I made this patch, which tackles a similar issue,
perhaps it's a good idea to merge both:
>From 7d6441fc6ec5ee7fe723e1ad86d11fdd17bee922 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio
Date
On 8/6/25 5:16 AM, Yongxing Mou wrote:
> The QCS8300 supports UBWC 4.0 and 4 channels LP5 memory interface. Use
> the SC8280XP as fallback for QCS8300 according to the specification.
>
> Signed-off-by: Yongxing Mou
> ---
Reviewed-by: Konrad Dybcio
Konrad
{ .name = "SH0", .buswidth = 16 },
> + { .name = "MC0", .buswidth = 4 },
> + {
> + .name = "ACV",
> + .fixed = true,
> + .perfmode = BIT(3),
> + .perfmode_bw = 1650,
Reviewed-by: Konrad Dybcio
Konrad
On 7/31/25 10:18 AM, Colin Ian King wrote:
> The pointer dev has been set to minor->dev, so replace minor->dev->dev
> with dev->dev in the DRM_DEV_ERROR messages.
>
> Signed-off-by: Colin Ian King
> ---
Reviewed-by: Konrad Dybcio
Konrad
("drm/msm: bail out late_init_minor() if it is not a GPU
> device")
> Signed-off-by: Colin Ian King
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 7/30/25 2:39 PM, Ayushi Makhija wrote:
> Currently, the high bitfield of certain DSI registers
> do not align with the configuration of the SWI registers
> description. This can lead to wrong programming these DSI
> registers, for example for 4k resloution where H_TOTAL is
> taking 13 bits but s
On 7/30/25 11:42 AM, Yongxing Mou wrote:
> The QCS8300 adopts UBWC 4.0, consistent with SA8775P, add 4 channels LP5
> configuration data according to the specification.
>
> Signed-off-by: Yongxing Mou
> ---
> drivers/soc/qcom/ubwc_config.c | 11 +++
> 1 file changed, 11 insertions(+)
>
On 7/29/25 11:49 PM, Akhil P Oommen wrote:
> On 7/30/2025 3:10 AM, Akhil P Oommen wrote:
>> On 7/29/2025 6:31 PM, Konrad Dybcio wrote:
>>> On 7/24/25 6:54 PM, Akhil P Oommen wrote:
>>>> On 7/24/2025 5:16 PM, Konrad Dybcio wrote:
>>>>> On 7/23/25 11:06
On 7/23/25 2:15 PM, Rob Clark wrote:
> On Wed, Jul 23, 2025 at 3:19 AM Konrad Dybcio
> wrote:
>>
>> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>>> CP_ALWAYS_ON counter falls under GX domain which is collapsed during
>>> IFPC. So switch to GMU_ALWAYS_ON counter f
On 7/24/25 6:54 PM, Akhil P Oommen wrote:
> On 7/24/2025 5:16 PM, Konrad Dybcio wrote:
>> On 7/23/25 11:06 PM, Akhil P Oommen wrote:
>>> On 7/22/2025 8:22 PM, Konrad Dybcio wrote:
>>>> On 7/22/25 3:39 PM, Dmitry Baryshkov wrote:
>>>>> On Sun, Jul 20, 2
On 7/23/25 11:06 PM, Akhil P Oommen wrote:
> On 7/22/2025 8:22 PM, Konrad Dybcio wrote:
>> On 7/22/25 3:39 PM, Dmitry Baryshkov wrote:
>>> On Sun, Jul 20, 2025 at 05:46:08PM +0530, Akhil P Oommen wrote:
>>>> There are some special registers which are accessible eve
On 7/23/25 9:28 PM, Akhil P Oommen wrote:
> On 7/23/2025 3:31 PM, Konrad Dybcio wrote:
>> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>>> A7XX_GEN2 generation has additional TCS slots. Poll the respective
>>> DRV status registers before pm suspend.
>>&g
MSM8916 / APQ8016, MSM8974 / APQ8074, MSM8226 and MSM8939.
>
> Fixes: 1924272b9ce1 ("soc: qcom: Add UBWC config provider")
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 7/22/25 11:37 PM, Akhil P Oommen wrote:
> On 7/22/2025 7:25 PM, Dmitry Baryshkov wrote:
>> On Sun, Jul 20, 2025 at 05:46:17PM +0530, Akhil P Oommen wrote:
>>> Add the IFPC restore register list and enable IFPC support on Adreno
>>> X1-85 gpu.
>>
>> Nit: GPU
>>
>> I can't stop but notice that KGS
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Now with IFPC, GX domain can collapse as soon as GPU becomes IDLE. So
> add gx_is_on check before accessing any GX registers during crashstate
> capture and recovery.
>
> Signed-off-by: Akhil P Oommen
> ---
[...]
> + /*
> + * This is true onl
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> When IFPC is supported, devfreq idling is redundant and adds
> unnecessary pm suspend/wake latency. So skip it when IFPC is
> supported.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/msm_gpu_devfreq.c | 6 ++
> 1 file changed, 6 ins
On 7/22/25 11:27 PM, Akhil P Oommen wrote:
> On 7/22/2025 7:19 PM, Dmitry Baryshkov wrote:
>> On Sun, Jul 20, 2025 at 05:46:12PM +0530, Akhil P Oommen wrote:
>>> Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support
>>> for a gpu. Based on this flag send the feature ctrl hfi message t
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support
> for a gpu. Based on this flag send the feature ctrl hfi message to
> GMU to enable IFPC support.
>
> Signed-off-by: Akhil P Oommen
> ---
[...]
> +static int a6xx_hfi_enable_ifpc(str
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> CP_ALWAYS_ON counter falls under GX domain which is collapsed during
> IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is
> not impacted by IFPC. Both counters are clocked by same xo clock source.
>
> Signed-off-by: Akhil P Oommen
>
On 7/22/25 9:47 PM, Akhil P Oommen wrote:
> On 7/22/2025 8:00 PM, Konrad Dybcio wrote:
>> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>>> A minor refactor to combine the subroutines for legacy a6xx GMUs under
>>> a single check. This helps to avoid an unnecessary check an
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Even though GX power domain is kept ON when there is a pending GPU
> interrupt, there is a small window of potential race with GMU where it
> may move the AHB fence to 'Drop' mode. Close this race window by polling
> for AHB fence to ensure that it is in
On 7/22/25 11:24 PM, Akhil P Oommen wrote:
> On 7/22/2025 7:14 PM, Dmitry Baryshkov wrote:
>> On Sun, Jul 20, 2025 at 05:46:09PM +0530, Akhil P Oommen wrote:
>>> Set Keepalive votes at appropriate places to block IFPC power collapse
>>> until we access all the required registers. This is required d
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> A7XX_GEN2 generation has additional TCS slots. Poll the respective
> DRV status registers before pm suspend.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16
> 1 file changed, 16 insertions(+)
>
>
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Add the IFPC restore register list and enable IFPC support on Adreno
> X1-85 gpu.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67
> ++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c |
On 7/22/25 3:39 PM, Dmitry Baryshkov wrote:
> On Sun, Jul 20, 2025 at 05:46:08PM +0530, Akhil P Oommen wrote:
>> There are some special registers which are accessible even when GX power
>> domain is collapsed during an IFPC sleep. Accessing these registers
>> wakes up GPU from power collapse and al
introduced all the way back in the initial
a7xx submission downstream, so I'll assume this concerns all SKUs
and this is a relevant fixes tag:
Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
Reviewed-by: Konrad Dybcio
Konrad
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> A minor refactor to combine the subroutines for legacy a6xx GMUs under
> a single check. This helps to avoid an unnecessary check and return
> early from the subroutine for majority of a6xx gpus.
>
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/dr
On 7/18/25 1:28 AM, Jessica Zhang wrote:
> The following chipsets support 2 total pixel streams:
> - sa8775p (on mdss_dp1)
> - sc8180x
> - sc8280xp (mdss_dp0-2 only)
> - sm8150
> - sm8350
I think 8250 can do 2 streams too, no?
sdm845/sm7150 also have the clocks for it FWIW, but that doe
On 7/17/25 10:27 PM, Jérôme de Bretagne wrote:
> On 2025/7/17 04:21, Xilin Wu wrote :
>>
>> On 2025/7/15 01:35:42, Dale Whinham wrote:
>>> From: Jérôme de Bretagne
>>>
>>> The OLED display in the Surface Pro 11 reports a maximum link rate of
>>> zero in its DPCD, causing it to fail to probe corre
On 7/16/25 5:00 PM, Dmitry Baryshkov wrote:
> On Wed, Jul 16, 2025 at 06:58:34PM +0530, Ling Xu wrote:
>> Domain ID in the uAPI is misleading. Remove checks and log messages
>> related to 'domain' field in capability structure. Update UAPI to
>> mark the field as unused.
>>
>> Signed-off-by: Ling X
r the kernel fault during init:
[...]
> Reported-by: Konrad Dybcio
> Fixes: 98659487b845 ("drm/msm: add support to take dpu snapshot")
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
l test robot
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202507150432.u0calr6w-...@intel.com/
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 7/14/25 10:08 PM, Rob Clark wrote:
> On Mon, Jul 14, 2025 at 12:56 PM Doug Anderson wrote:
>>
>> Hi,
>>
>> On Mon, Jun 30, 2025 at 9:15 AM Akhil P Oommen
>> wrote:
>>>
>>> On 6/30/2025 9:26 PM, Konrad Dybcio wrote:
>>>>
>
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