cmdq_mbox_priv of cmdq_pkt and then add it to the DRAM
address when generating instructions to ensure GCE accesses the correct
DRAM address. CMDQ users can then call CMDQ helper APIs as usual.
Signed-off-by: Jason-JH Lin
Reviewed-by: AngeloGioacchino Del Regno
Il 27/08/25 13:37, Jason-JH Lin ha scritto:
GCE can only fetch the command buffer address from a 32-bit register.
Some SoCs support a 35-bit command buffer address for GCE, which
requires a right shift of 3 bits before setting the address into
the 32-bit register. A comment has been added to the
resource leakage.
Signed-off-by: Jason-JH Lin
Reviewed-by: AngeloGioacchino Del Regno
Il 06/10/25 14:16, Nicolas Frattaroli ha scritto:
On Monday, 6 October 2025 13:37:28 Central European Summer Time
AngeloGioacchino Del Regno wrote:
Il 06/10/25 12:58, Nicolas Frattaroli ha scritto:
On Friday, 3 October 2025 23:41:16 Central European Summer Time Chia-I Wu wrote:
On Fri, Oct 3
controller takes care of the regulators and PLL clock frequencies
to squeeze the maximum amount of power out of the silicon.
Add a binding which models it as a power domain.
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
Il 06/10/25 12:58, Nicolas Frattaroli ha scritto:
On Friday, 3 October 2025 23:41:16 Central European Summer Time Chia-I Wu wrote:
On Fri, Oct 3, 2025 at 1:16 PM Nicolas Frattaroli
wrote:
Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics"
by MediaTek. On the MT8196 and MT
t;drm/mediatek: clean up driver data initialisation")
Signed-off-by: Sjoerd Simons
Reviewed-by: AngeloGioacchino Del Regno
Il 29/09/25 09:46, Nicolas Frattaroli ha scritto:
Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics"
by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this
integration silicon is required to power on the GPU.
This glue silicon is in the form of an embedded microco
Il 25/09/25 03:09, Dmitry Baryshkov ha scritto:
On Wed, Sep 24, 2025 at 12:37:06PM +0200, AngeloGioacchino Del Regno wrote:
During probe, this driver is registering two platform devices: one
for the HDMI Codec driver and one for the DisplayPort PHY driver.
In the probe function, none of the
the common mailbox framework.
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
Il 23/09/25 13:39, Nicolas Frattaroli ha scritto:
On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled
by some integration logic, referred to as "MFlexGraphics" by MediaTek,
which comes in the form of an embedded controller running
special-purpose firmware.
This controller ta
Il 23/09/25 17:23, Johan Hovold ha scritto:
This series fixes various probe resource leaks in the mediatek drm
drivers that were found through inspection.
Johan
Whole series is
Reviewed-by: AngeloGioacchino Del Regno
e086 ("drm/mediatek: dp: Audio support for MT8195")
Fixes: caf2ae486742 ("drm/mediatek: dp: Add support for embedded DisplayPort
aux-bus")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dp.c | 30 ++
1 file changed, 26 inser
Il 23/09/25 13:40, Nicolas Frattaroli ha scritto:
Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics"
by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this
integration silicon is required to power on the GPU.
This glue silicon is in the form of an embedded microco
Reviewed-by: AngeloGioacchino Del Regno
---
.../bindings/soc/mediatek/mediatek,pwrap.yaml | 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,
Il 18/09/25 09:01, CK Hu (胡俊光) ha scritto:
Hi, Rob and Krzysztof:
On Thu, 2025-08-28 at 16:06 +0800, Paul Chen wrote:
From: Paul-pl Chen
Add mediatek,exdma.yaml to support EXDMA for MT8196.
The MediaTek display overlap extended DMA engine, namely
OVL_EXDMA or EXDMA, primarily functions as a D
that I have here is about the "no_clocks" name, as it may be read
as "number of clocks" ("no" is often used as "number").
I don't really have any better name to suggest though, and the execution is
right,
so.
Reviewed-by: AngeloGioacchino Del Regno
Cheers,
Angelo
Controller
+
+maintainers:
+ - Nicolas Frattaroli
+
+properties:
+ compatible:
+enum:
+ - mediatek,mt8196-gpueb-mbox
Before anyone asks - yes, it is 100% sure that SoCs will be added here sooner or
later.
Reviewed-by: AngeloGioacchino Del Regno
the common mailbox framework.
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
r
like the OPP table can be read.
Acked-by: Rob Herring (Arm)
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
Il 15/09/25 15:32, Nicolas Frattaroli ha scritto:
On Monday, 15 September 2025 12:28:09 Central European Summer Time
AngeloGioacchino Del Regno wrote:
Il 12/09/25 20:37, Nicolas Frattaroli ha scritto:
MediaTek uses some glue logic to control frequency and power on some of
their GPUs. This is
and expose it through a
helper function to the rest of panthor.
Reviewed-by: Steven Price
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
devfreq can use it as well.
Reviewed-by: Steven Price
Signed-off-by: Nicolas Frattaroli
Reviewed-by: AngeloGioacchino Del Regno
Il 12/09/25 20:37, Nicolas Frattaroli ha scritto:
On the MediaTek MT8196 SoC, the GPU has its power and frequency
dynamically controlled by an embedded special-purpose MCU. This MCU is
in charge of powering up the GPU silicon. It also provides us with a
list of available OPPs at runtime, and is f
Il 12/09/25 20:37, Nicolas Frattaroli ha scritto:
MediaTek uses some glue logic to control frequency and power on some of
their GPUs. This is best exposed as a devfreq driver, as it saves us
from having to hardcode OPPs into the device tree, and can be extended
with additional devfreq-y logic lik
s not garbled (so, to help testing display
support in an automated manner).
--
2.49.0
---
AngeloGioacchino Del Regno (9):
drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility
drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata
drm/mediatek: mtk_hdmi:
Il 04/08/25 11:02, AngeloGioacchino Del Regno ha scritto:
Il 24/07/25 11:14, Krzysztof Kozlowski ha scritto:
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The dual and triple core jpeg encoder and decoder (respectively)
on MT8195 are far apart: the only way to have this to make sense
Il 11/09/25 17:10, Ariel D'Alessandro ha scritto:
Convert the existing text-based DT bindings for MELFAS MIP4 Touchscreen
controller to a DT schema.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Rob Herring (Arm)
Reviewed-by: AngeloGioacchino Del Regno
Il 12/09/25 10:27, Chen-Yu Tsai ha scritto:
On Fri, Sep 12, 2025 at 2:06 PM Krzysztof Kozlowski wrote:
On Thu, Sep 11, 2025 at 12:09:50PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
Path to a DT schema.
Signed-off-by: Ariel D'Al
Il 11/09/25 17:09, Ariel D'Alessandro ha scritto:
Current, the DT bindings for MediaTek's MT65xx Pin controller is missing
the gpio-line-names property, add it to the associated schema.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
---
(Arm)
Reviewed-by: AngeloGioacchino Del Regno
Il 11/09/25 17:09, Ariel D'Alessandro ha scritto:
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
Path to a DT schema.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
---
.../bindings/media/mediatek,mt8173-mdp.ya
andro
Reviewed-by: AngeloGioacchino Del Regno
B])$":
+type: object
+$ref: regulator.yaml#
+unevaluatedProperties: false
+description: |
Please drop the vertical bar | from all descriptions
after which,
Reviewed-by: AngeloGioacchino Del Regno
+ Properties for a single BUCK regula
Il 11/09/25 17:09, Ariel D'Alessandro ha scritto:
Convert the existing text-based DT bindings for Mediatek MT8173 Video
Processor Unit to a DT schema.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
---
.../bindings/media/mediatek,mt8173-vpu.y
Il 28/08/25 10:07, Paul Chen ha scritto:
From: Nancy Lin
Ovlsys_adaptor is an encapsulated module designed to
simplify the DRM control flow. This module is composed
of 20 EXDMAs, 20 BLENDERs, and 12 OUTPROCs.
Two EXDMAs merge into one layer, allowing the module
to support 20 layers for 3 displa
Il 28/08/25 10:07, Paul Chen ha scritto:
From: Nancy Lin
To support multiple mmsys instances in the one mediatek-drm instance,
providing improved flexibility and scalability by the following changes:
1. Add DDP_COMPONENT_DRM_OVLSYS_ADAPTOR* to probe the
ovlsys_adaptor drivers and support di
Johan Hovold (2):
drm/mediatek: fix potential OF node use-after-free
drm/mediatek: clean up driver data initialisation
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
The whole series is
Reviewed-by: AngeloGioacchino Del
Il 08/09/25 14:05, Nicolas Frattaroli ha scritto:
On Monday, 8 September 2025 12:06:01 Central European Summer Time
AngeloGioacchino Del Regno wrote:
Il 05/09/25 12:23, Nicolas Frattaroli ha scritto:
The MT8196 SoC uses an embedded MCU to control frequencies and power of
the GPU. This
Il 05/09/25 12:23, Nicolas Frattaroli ha scritto:
The MT8196 SoC uses an embedded MCU to control frequencies and power of
the GPU. This controller is referred to as "GPUEB".
It communicates to the application processor, among other ways, through
a mailbox.
The mailbox exposes one interrupt, whi
Il 08/09/25 13:39, Nicolas Frattaroli ha scritto:
On Monday, 8 September 2025 13:15:03 Central European Summer Time
AngeloGioacchino Del Regno wrote:
Il 05/09/25 12:22, Nicolas Frattaroli ha scritto:
On the MediaTek MT8196 SoC, the GPU has its power and frequency
dynamically controlled by an
Il 05/09/25 12:22, Nicolas Frattaroli ha scritto:
On the MediaTek MT8196 SoC, the GPU has its power and frequency
dynamically controlled by an embedded special-purpose MCU. This MCU is
in charge of powering up the GPU silicon. It also provides us with a
list of available OPPs at runtime, and is f
67-1-jason-jh@mediatek.com
For the entire series:
Reviewed-by: AngeloGioacchino Del Regno
Il 24/07/25 11:12, Krzysztof Kozlowski ha scritto:
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adda6_adc_clk
Il 24/07/25 11:14, Krzysztof Kozlowski ha scritto:
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The dual and triple core jpeg encoder and decoder (respectively)
on MT8195 are far apart: the only way to have this to make sense
is to split those in multiple address ranges in device
Please, remove that bogus "20220315152503 created" user that does not exist.
After which:
Reviewed-by: AngeloGioacchino Del Regno
Il 03/08/25 00:23, Dmitry Baryshkov ha scritto:
On Tue, Apr 15, 2025 at 12:42:58PM +0200, AngeloGioacchino Del Regno wrote:
This series adds support for the HDMI-TX v2 Encoder and DDCv2, and for
the direct connection DPI as found in MT8195, MT8188 and their variants.
Angelo, just wanted to
Il 25/07/25 15:52, Rob Herring ha scritto:
On Thu, Jul 24, 2025 at 3:39 AM AngeloGioacchino Del Regno
wrote:
As Rob pointed out, MediaTek devicetrees are *poor* in the dtbs_check
tests, and got an infinite load of warnings.
This series starts attacking this situation.
I didn't really
ned-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts
index 08b3b0827436..30
"-SBC-i1200")
Signed-off-by: AngeloGioacchino Del Regno
---
.../mediatek/mt8395-kontron-3-5-sbc-i1200.dts| 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
b/arch/arm64/boot/dts/mediatek/m
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index d40f4c1b9766..b3761b80cac7 100644
--- a/
This devicetree contained only the SoC compatible but lacked the
machine specific one: add a "mediatek,mt8516-pumpkin" compatible
to the list to fix dtbs_check warnings.
Fixes: 9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts")
Signed-off-by: AngeloGioacchino Del Reg
ot;jpeg-encoder@1a03" respectively, and change their
children to use the newly defined ranges.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 +---
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm
Fix the pinctrl node names to adhere to the bindings, as the main
pin node is supposed to be named like "uart0-pins" and the pinmux
node named like "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
---
.../boot/dts/mediatek/pumpkin-common.dtsi | 18 +-
Move the VBAT supply to mt8195-cherry-tomato-{r1,r2} as this power
supply is named like that only for the Realtek RT5682i codec.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2
to hook the display controller of the SoC to their
specific output port(s).
Signed-off-by: AngeloGioacchino Del Regno
---
.../boot/dts/mediatek/mt8183-pumpkin.dts | 8 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 239 +-
2 files changed, 238 insertions(+), 9 deletions
readability, move the entire panel node declaration to each
of the relevant Kukui machine dtsi: even though this introduces
some duplication, the advantages in readability surclass that.
Signed-off-by: AngeloGioacchino Del Regno
---
.../dts/mediatek/mt8183-kukui-jacuzzi.dtsi| 5
.../dts
Add a power supply for the Cache Coherent Interconnect node as it
is required to perform CPU DVFS because both are scaling together.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64
Fix the pinctrl node names to adhere to the bindings, as the main
pin node is supposed to be named like "uart0-pins" and the pinmux
node named like "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
---
.../mediatek/mt8183-kukui-audio-da7219.dtsi | 4 +-
.../mediate
range of t-phy.
Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1")
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm6
Fix the pinctrl node names to adhere to the bindings, as the main
pin node is supposed to be named like "uart0-pins" and the pinmux
node named like "pins-bus".
While at it, also cleanup all of the MTK_DRIVE_(x)mA by changing
that to just the (x) number.
Signed-off-by: Angelo
slot, SDIO")
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5
: AngeloGioacchino Del Regno
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts| 38 +++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 03cc48321a3f..fccb948cfa45 100644
--- a
The binding wants the node to be named "i2c-number", alternatively
"i2c@address", but those are named "i2c-gpio-number" instead.
Rename those to i2c-0, i2c-1 to adhere to the binding and suppress
dtbs_check warnings.
Signed-off-by: AngeloGioacchino Del Regno
---
check warning.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r
-phy.
Fixes: 963c3b0c47ec ("arm64: dts: mediatek: fix t-phy unit name")
Fixes: 918aed7abd2d ("arm64: dts: mt7986: add pcie related device nodes")
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 ++--
1 file changed, 6 insert
The sysirq has "intpol-controller" as node name, but being this an
interrupt controller, it needs to be named "interrupt-controller"
as per what the bindings (correctly) expect.
This commit brings no functional changes, but fixes a dtbs_check
warning.
Signed-off-by: Angelo
Change the pinctrl node names to adhere to the binding: the main
nodes are now named like "uart0-pins" and the children "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt6797.dtsi | 40
1 file changed,
The "M4U" IOMMU requires a handle to the infracfg to switch to
the 4gb/pae addressing mode: add it.
Signed-off-by: AngeloGioacchino Del Regno
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/
All of the I2C nodes in this devicetree has a bogus "id" property,
which was probably specifying the I2C bus number.
This property was never parsed and never used - and besides, it
also gives dtbs_check warnings: remove it from all i2c nodes.
Signed-off-by: AngeloGioacchino Del Regno
The node names for "pmic", "regulators", "rtc", and "keys" are
dictated by the PMIC MFD binding: change those to adhere to it.
Fixes: aef783f3e0ca ("arm64: dts: mediatek: Add MT6331 PMIC devicetree")
Signed-off-by: AngeloGioacchino Del Regno
jpegenc bindings to allow specifying
children nodes such as "jpegdec@0,1", "jpegdec@1,0" or for
encoder "jpegenc@0,0", "jpegenc@1,0" to resolve dtbs_check issues.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/media/mediatek,mt8195-
split
the mt8195/8188 conditionals to allow specifying only the cfg MMIO
on MT8188.
Fixes: 91e0d560b9fd ("dt-bindings: remoteproc: mediatek: Support MT8188
dual-core SCP")
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/remoteproc/mtk,scp.yaml | 23 ---
clock output name on all of the
HDMI PHY IPs that are perfectly compatible with MT8195.
Fixes: c78fe548b062 ("dt-bindings: phy: mediatek: hdmi-phy: Add mt8195
compatible")
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/phy/mediatek,hdmi-phy.yaml | 25 +
t;)
Signed-off-by: AngeloGioacchino Del Regno
---
.../regulator/mediatek,mt6331-regulator.yaml | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml
b/Documentation/devicetree/bindings
This binding had no compatible and for this reason would not be
applied to anything: add the missing "mediatek,mt6331-regulator"
comaptible.
Fixes: 6385e21692bb ("regulator: Add bindings for MT6331 regulator")
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/regul
This binding had no compatible and for this reason would not be
applied to anything: add the missing "mediatek,mt6332-regulator"
compatible.
Fixes: e22943e32e1f regulator: ("Add bindings for MT6332 regulator")
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/regul
Allow node names like "uart0-pins" for the main nodes and "pins-bus"
for the children to make this binding consistent with the majority
of the other MediaTek pinctrl bindings.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/pinctrl/mediatek,mt67
crement maxItems for reg to two.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
b/Documentat
ek MT7968A and MT7986B SoCs do
not have those two interrupts hooked up to their irq controlller.
For this reason, make the EIP and MEM interrupt optional.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/crypto/inside-secure,safexcel.yaml | 2 ++
1 file changed, 2
Add a compatible for the General Purpose Timer (GPT) found on the
MediaTek Helio X10 MT6795 SoC which is fully compatible with the
one found in MT6577.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 +
1 file changed, 1 insertion
The MT7622 SoC has a PWM channel 7-2 group for the pwm7 IP: add
the missing pwm_ch7_2 group.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation
The GCE Mailbox needs only one clock and the clock-names can be
used only by the driver (which, for instance, does not use it),
and this is true for all of the currently supported MediaTek SoCs.
Stop requiring to specify clock-names on all non-MT8195 GCEs.
Signed-off-by: AngeloGioacchino Del
Both clocks and clock-names are missing (a lot of) entries: add
all the used audio clocks and their description and also fix the
example node.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/sound/mt8192-afe-pcm.yaml| 106 +-
1 file changed, 104 insertions
Like others, the MediaTek DisplayPort controller provides an
auxiliary bus: import the common dp-aux-bus.yaml in this binding
to allow specifying an aux-bus subnode.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/display/mediatek/mediatek,dp.yaml | 3 +++
1 file
and reset-names on
all MediaTek SoCs.
Those properties are optional because there are multiple ways to
reset this IP and the reset lines in MM/VDO are used only if the
IP cannot perform warm-reset.
Signed-off-by: AngeloGioacchino Del Regno
---
.../devicetree/bindings/display/mediatek/mediatek
n any case.
More will come, but I'll be on a long holiday soon, so not from me
(or anyway not before I come back anyway), but most probably from
someone else (in August...!).
Cheers!
Angelo
AngeloGioacchino Del Regno (38):
dt-bindings: display: mediatek: dpi: Allow specifying resets
dt-bi
d
post-disable")
Signed-off-by: Louis-Alexis Eyraud
Reviewed-by: AngeloGioacchino Del Regno
---
This patch fixes an issue that can be observed on boards such as
MediatekGenio 1200-EVK or 350-EVK with a kernel based on linux-next
(tag: next-20250635) since commit c9b1150a68d9 ("drm/atomi
hich I was thinking that was already properly
implemented
for MediaTek drivers.
Apparently it's not true for *all* of them... but then, just keeping things
ordered
by preference is a simpler solution and probably the best one for now.
Reviewed-by: AngeloGioacchino Del Regno
has been added to wait for the
ddp_cmdq_cb() callback,indicating that the GCE IRQ has been triggered.
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Jason-JH Lin
Reviewed-by: AngeloGioacchino Del Regno
On Mon, 12 May 2025 18:49:24 +0530, Vignesh Raman wrote:
> The mediatek display driver fails to probe on mt8173-elm-hana and
> mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY
> configurations.
>
> Commit 924d66011f24 ("drm/mediatek: stop selecting foreign drivers")
> stopped sel
lecting foreign drivers")
Reviewed-by: Nícolas F. R. A. Prado
Signed-off-by: Vignesh Raman
Reviewed-by: AngeloGioacchino Del Regno
: Louis-Alexis Eyraud
Reviewed-by: AngeloGioacchino Del Regno
On Thu, 24 Apr 2025 09:08:48 +0800, Jianeng Ceng wrote:
> This is v11 of the MT8186 Chromebook device tree series.
>
Applied to v6.15-next/dts64, thanks!
[1/2] dt-bindings: arm: mediatek: Add MT8186 Ponyta Chromebook
commit: ce8ec1f8c8b363c2511332c909d06df7ae01f1b3
[2/2] arm64: dts: mediat
Il 24/04/25 03:08, Jianeng Ceng ha scritto:
Ponyta is a custom label Chromebook based on MT8186. It is a
self-developed project of Huaqin and has no fixed OEM.
Signed-off-by: Jianeng Ceng
Reviewed-by: AngeloGioacchino Del Regno
---
Changes in v11:
- PATCH 1/2: Remove redundant items
e assignment into a single variable
assignment, which states that the configuration is valid when there are
not all zeros, clearing up the warning since the variable will always be
initialized.
Fixes: 38d42c261389 ("drm: panel: Add driver for Himax HX8279 DDIC panels")
Suggested-by: Angelo
valid != goa_even_valid)
| ^~
Change the initialization to set it to the value of the condition instead.
Fixes: 38d42c261389 ("drm: panel: Add driver for Himax HX8279 DDIC panels")
Signed-off-by: Arnd Bergmann
Reviewed-by: AngeloGioacchino De
initialized-207354fb930c
Best regards,
Reviewed-by: Neil Armstrong
I'll wait a few days until AngeloGioacchino Del Regno reviews it to be sure
it's the right fix.
Thanks,
Neil
I would prefer
if (num_zero == ARRAY_SIZE(desc->goa_odd_timing))
Il 23/04/25 11:36, Jianeng Ceng ha scritto:
Ponyta is a custom label Chromebook based on MT8186. It is a
self-developed project of Huaqin and has no fixed OEM.
Signed-off-by: Jianeng Ceng
---
Changes in v10:
- PATCH 1/2: Add enum for ponyta sku.
- Link to
v9:https://lore.kernel.org/all/2025032
Il 21/04/25 21:16, Dmitry Baryshkov ha scritto:
On Tue, Apr 15, 2025 at 12:43:20PM +0200, AngeloGioacchino Del Regno wrote:
Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their variants, and
including support for display modes up to
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