Hi Ao,
kernel test robot noticed the following build errors:
[auto build test ERROR on 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab]
url:
https://github.com/intel-lab-lkp/linux/commits/Ao-Xu-via-B4-Relay/dt-bindings-display-meson-dw-hdmi-Add-compatible-for-S4-HDMI-controller/20250110-134113
Hi Wayne,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-exynos/exynos-drm-next linus/master
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-misc/drm-misc-next
drm-tip/drm-tip v6.13-rc6 next-20250110
Hi Ao,
kernel test robot noticed the following build errors:
[auto build test ERROR on 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab]
url:
https://github.com/intel-lab-lkp/linux/commits/Ao-Xu-via-B4-Relay/dt-bindings-display-meson-dw-hdmi-Add-compatible-for-S4-HDMI-controller/20250110-134113
Use the correct format for all kernel-doc comments.
Use structname.membername for named structs.
Don't precede function names in kernel-doc with '@' sign.
Use the correct function parameter names in kernel-doc comments.
This fixes around 80 kernel-doc warnings.
Signed-off-by: Randy Dunlap
Cc: Bo
Hi Wayne,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-exynos/exynos-drm-next linus/master v6.13-rc6
next-20250110]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch
On 1/10/25 9:16 AM, Joel Granados wrote:
> Add the const qualifier to all the ctl_tables in the tree except for
> watchdog_hardlockup_sysctl, memory_allocation_profiling_sysctls,
> loadpin_sysctl_table and the ones calling register_net_sysctl (./net,
> drivers/inifiniband dirs). These are specia
From: "Paul-pl.Chen"
Add support multiple mmsys instances in the one mediatek-drm instance.
Nancy.Lin (7):
soc: mediatek: add mmsys support for MT8196
soc: mediatek: mutex: add mutex support for MT8196
drm/mediatek: add EXDMA support for MT8196
drm/mediatek: add BLENDER support for MT819
From: "Paul-pl.Chen"
Add mediatek,exdma.yaml to support EXDMA for MT8196.
Signed-off-by: Paul-pl.Chen
---
The header used in examples:
#include
#include
are not upstreamed yet.
It will be sent by related owner soon.
---
.../display/mediatek/mediatek,exdma.yaml | 77 +++
From: "Nancy.Lin"
To support multiple mmsys instances in the one mediatek-drm instance,
providing improved flexibility and scalability by the following changes:
1. Defined new DRM component IDs DDP_COMPONENT_DRM_OVLSYS_ADAPTOR*
to support different mmsys composition.
2. Added new component typ
From: "Nancy.Lin"
Ovlsys_adaptor is an encapsulated module designed to
simplify the DRM control flow. This module is composed
of 20 EXDMAs, 20 BLENDERs, and 12 OUTPROCs.
Two EXDMAs merge into one layer, allowing the module
to support 20 layers for 3 display paths.
Ovlsys_adaptor driver is integra
From: "Paul-pl.Chen"
Add mediatek,exdma.yaml to support EXDMA for MT8196.
Signed-off-by: Paul-pl.Chen
---
The header used in examples:
#include
#include
are not upstreamed yet.
It will be sent by related owner soon.
---
.../display/mediatek/mediatek,exdma.yaml | 77 +++
From: "Paul-pl.Chen"
Add mediatek,blender.yaml to support BLENDER for MT8196.
Signed-off-by: Paul-pl.Chen
---
The header used in examples:
#include
is not upstreamed yet.
It will be sent by related owner soon.
---
.../display/mediatek/mediatek,blender.yaml| 50 +++
1 fil
From: "Paul-pl.Chen"
Add mediate,outproc.yaml to support OUTPROC for MT8196.
Signed-off-by: Paul-pl.Chen
---
The header used in examples:
#include
is not upstreamed yet.
It will be sent by related owner soon.
---
.../display/mediatek/mediatek,outproc.yaml| 57 +++
1 fil
From: "Paul-pl.Chen"
Add compatible string to support mutex for MT8196.
Signed-off-by: Paul-pl.Chen
---
.../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
b/Do
From: "Nancy.Lin"
OUTPROC handles the post-stage of pixel processing in
the overlapping procedure.OUTPROC manages pixels for
gamma correction and ensures that pixel values are
within the correct range.
Signed-off-by: Nancy.Lin
Signed-off-by: Paul-pl.Chen
---
drivers/gpu/drm/mediatek/Makefile
From: "Nancy.Lin"
Add mutex support the main and external display for MT8196.
Signed-off-by: Nancy.Lin
Signed-off-by: Paul-pl.Chen
---
drivers/soc/mediatek/mtk-mutex.c | 233 +++--
include/linux/soc/mediatek/mtk-mutex.h | 2 +
2 files changed, 222 insertions(+), 13
From: "Nancy.Lin"
EXDMA is a DMA engine for reading data from DRAM with
various DRAM footprints and data formats. For input
sources in certain color formats and color domains,
EXDMA also includes a color transfer function to
process pixels into a consistent color domain.
Signed-off-by: Nancy.Lin
From: "Nancy.Lin"
BLENDER executes the alpha blending function for overlapping
layers from different sources, which is the primary function
of the overlapping system.
Signed-off-by: Nancy.Lin
Signed-off-by: Paul-pl.Chen
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/
From: "Nancy.Lin"
1. Defining driver data and adding compatible string
for different subsystems
(DISPSYS0, DISPSYS1, OVLSYS0, OVLSYS1, VDISP_AO)
2. Adding functions to control top clocks and ddp clocks.
3. Updating the probe function to initialize clocks and
enable runtime PM if its node has the
From: "Paul-pl.Chen"
Add compatible for mmsys yaml of MT8196
Signed-off-by: Paul-pl.Chen
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
b/Documentation
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
Rename the debugfs files to match their purpose and the patter provided
by other bandwidth and clock-related files:
threshold_high -> max_core_ab
threshold_low -> low_core_ab
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu
On 1/9/2025 6:02 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 05:40:23PM -0800, Abhinav Kumar wrote:
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The fix_core_ab_vote is an average bandwidth value, used for bandwidth
overrides in several cases. However there is an internal inconsist
On Fri, 10 Jan 2025 20:19:47 +0100
Simona Vetter wrote:
> Hm, unless a drivers vblank handling code is extremely fun, there should
> be absolutely no memory allocations or user copies in there at all. Hence
> I think you're papering over a real bug here. The vblank itself should be
> purely a fre
Default SLPC power profile is Base(0). Power Saving mode(1)
has conservative up/down thresholds and is suitable for use with
apps that typically need to be power efficient.
Selected power profile will be displayed in this format-
$ cat slpc_power_profile
[base]power_saving
$ echo power_sa
meson/meson_venc.c | 346 ++-
> drivers/gpu/drm/meson/meson_venc.h |4 +-
> drivers/gpu/drm/meson/meson_viu.c |9 +-
> drivers/gpu/drm/meson/meson_vpp.c | 12 +-
> 19 files changed, 1865 insertions(+), 403 deletions(-)
&g
On Fri, Jan 10, 2025 at 1:53 PM Ian Forbes wrote:
>
> Adds a new BO param that keeps the reservation locked after creation.
> This removes the need to re-reserve the BO after creation which is a
> waste of cycles.
>
> This also fixes a bug in vmw_prime_import_sg_table where the imported
> reservat
On 1/9/2025 6:10 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 05:50:16PM -0800, Jessica Zhang wrote:
On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM
sconnected.
drm_connector_hdmi_audio_plugged_notify(connector, false);
+ return;
}
if (connector->hdmi.funcs->read_edid)
---
base-commit: 1854df7087be70ad54e24b2e308d7558ebea9f27
change-id: 20250110-hdmi-conn-edid-read-fix-178513c2b7ea
On 12/19/24 10:03, Simona Vetter wrote:
On Thu, Dec 19, 2024 at 09:02:27AM +, Daniel Stone wrote:
On Wed, 18 Dec 2024 at 10:32, Brian Starkey wrote:
On Wed, Dec 18, 2024 at 11:24:58AM +, Simona Vetter wrote:
For that reason I think linear modifiers with explicit pitch/size
alignment c
On Tue, Dec 17, 2024 at 03:33:23PM -0800, Matthew Brost wrote:
> This patch introduces support for GPU Shared Virtual Memory (SVM) in the
> Direct Rendering Manager (DRM) subsystem. SVM allows for seamless
> sharing of memory between the CPU and GPU, enhancing performance and
> flexibility in GPU c
On Thu, Jan 09, 2025 at 09:09:46AM +0100, Christian König wrote:
> Answering on my reply once more as pure text mail.
It is hard to do anything with your HTML mails :\
> > Well you were also the person who mangled the struct page pointers in
> > the scatterlist because people were abusing this an
The pull request you sent on Sat, 11 Jan 2025 06:28:19 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2025-01-11
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/e0daef7de1acecdb64c1fa31abc06529abb98710
Thank you!
--
Deet-doot-dot, I am a bot.
h
On Fri, Jan 10, 2025 at 08:34:55PM +0100, Simona Vetter wrote:
> So if I'm getting this right, what you need from a functional pov is a
> dma_buf_tdx_mmap? Because due to tdx restrictions, the normal dma_buf_mmap
> is not going to work I guess?
Don't want something TDX specific!
There is a gener
Hi Linus,
Regular weekly fixes, this has the usual amdgpu/xe/i915 bits. There is
a bigger bunch of mediatek patches that I considered not including at
this stage, but all the changes (except for one were obvious small
fixes, and the rotation one is a few lines, and I suppose will help
someone have
On Fri, Jan 10, 2025 at 08:24:22PM +0100, Simona Vetter wrote:
> On Thu, Jan 09, 2025 at 01:56:02AM +0800, Xu Yilun wrote:
> > > > > 5) iommufd and kvm are both using CPU addresses without DMA. No
> > > > > exporter mapping is possible
> > > >
> > > > We have customers using both KVM and XEN with
On Thu, Jan 09, 2025 at 07:06:48AM +0800, Xu Yilun wrote:
> > So I guess my first question is, which locking rules do you want here for
> > pfn importers?
> >
> > follow_pfn() is unwanted for private MMIO, so dma_resv_lock.
> >
> >As Sima explained you either have follow_pfn() and mmu_noti
On Thu, Jan 09, 2025 at 01:56:02AM +0800, Xu Yilun wrote:
> > > > 5) iommufd and kvm are both using CPU addresses without DMA. No
> > > > exporter mapping is possible
> > >
> > > We have customers using both KVM and XEN with DMA-buf, so I can clearly
> > > confirm that this isn't true.
> >
> > To
On Fri, Jan 10, 2025 at 04:49:13PM +, Vitaliy Shevtsov wrote:
> drm_wait_one_vblank() uses drm_WARN() to check for a time-dependent
> condition. Since syzkaller runs the kernel with the panic_on_warn set, this
> causes the entire kernel to panic with a "vblank wait timed out on crtc %i"
> messa
On Wed, Jan 08, 2025 at 08:34:28PM +0200, Dmitry Baryshkov wrote:
> On Wed, Jan 08, 2025 at 06:24:16PM +0100, Simona Vetter wrote:
> > msm is automagically upgrading normal commits to full modesets, and
> > that's a big no-no:
> >
> > - for one this results in full on->off->on transitions on all t
On Thu, Jan 09, 2025 at 03:45:53PM +, Daniel Stone wrote:
> Hi,
>
> On Thu, 9 Jan 2025 at 15:30, Michel Dänzer wrote:
> > On 2025-01-08 18:22, Simona Vetter wrote:
> > > Maybe I'm wrong, but my understanding is that English generally doesn't do
> > > compound words connected with dashes, you
Adds a new BO param that keeps the reservation locked after creation.
This removes the need to re-reserve the BO after creation which is a
waste of cycles.
This also fixes a bug in vmw_prime_import_sg_table where the imported
reservation is unlocked twice.
Signed-off-by: Ian Forbes
Fixes: b32233
On Thu, Jan 9, 2025 at 10:03 AM Thomas Zimmermann wrote:
>
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
> and buffer size. No alignment required.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Zack Rusin
> Cc: Broadcom internal kernel review list
>
> ---
> drivers/gpu/drm/vmw
On 12/4/24 04:31, Tomi Valkeinen wrote:
> Fix "mapping sg segment longer than device claims to support" warning by
> setting the max segment size.
>
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu
On Tue, Dec 17, 2024 at 03:58:46PM +0100, Thomas Hellström wrote:
> Simplify the pool allocation code somewhat by merging loop arguments
> used by multiple functions together in a struct and simplifying the
> loop. Also add documentation.
> This hopefully makes the behaviour of the allocation loop
On Thu, Jan 09, 2025 at 03:40:59PM -0500, Alex Deucher wrote:
> Possibly fixed by this patch?
> https://lore.kernel.org/lkml/CAJZ5v0i=ap+w4QZ8f2DsaHY6D=XUEuSNjyQ-2_=dgolfzjd...@mail.gmail.com/T/
Yap, it does.
You can add
Reported-by: Borislav Petkov (AMD)
Tested-by: Borislav Petkov (AMD)
if y
Hi Dave, Simona,
Updates for 6.14.
The following changes since commit 695c2c745e5dff201b75da8a1d237ce403600d04:
drm/amdgpu: Handle NULL bo->tbo.resource (again) in amdgpu_vm_bo_update
(2024-12-18 12:39:08 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/
On Fri, Jan 10, 2025 at 09:16:44AM +, Tvrtko Ursulin wrote:
>
> On 09/01/2025 19:59, Matthew Brost wrote:
> > On Wed, Jan 08, 2025 at 06:55:16PM +, Tvrtko Ursulin wrote:
> > >
> > > On 08/01/2025 16:57, Danilo Krummrich wrote:
> > > > On Wed, Jan 08, 2025 at 03:13:39PM +, Tvrtko Ursul
On Thu, 09 Jan 2025 05:16:39 -0800, Joel Granados wrote:
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 2406cda75b7b..5384d1bb4923 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4802,7 +4802,7 @@ int i9
On 08/01/2025 18:35, Tvrtko Ursulin wrote:
> Instead of manually peeking into the DRM scheduler implementation details
> lets use the previously added helper.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Christian König
> Cc: Danilo Krummrich
> Cc: Matthew Brost
> Cc: Philipp Stanner
> Cc: Frank B
On 08/01/2025 18:35, Tvrtko Ursulin wrote:
> Lets isolate scheduler internals from drivers such as pvr which currently
> walks the dependency array to look for fences.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Christian König
> Cc: Danilo Krummrich
> Cc: Matthew Brost
> Cc: Philipp Stanner
Rev
This controller support scalable data lanes from 1 to 4. Add the
'data-lanes' property to configure the number of MIPI display panel lanes
selected for boards.
Change $ref of port@1 from 'port' to 'port-base' and add 'endpoint'
property referencing video-interfaces.yaml. Allow 'data-lanes' values
On Thu, 09 Jan 2025 12:34:57 +0100, Jonas Rebmann wrote:
> Add DataImage FG080016DNCWAG03 8" 640x480 TFT LCD panel compatible
> string.
>
> Signed-off-by: Jonas Rebmann
> ---
> Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked
On Wed, 08 Jan 2025 12:27:18 +0100, AngeloGioacchino Del Regno wrote:
> Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
> and MT8188 SoCs.
>
> This fully supports the HDMI Specification 2.0b, hence it provides
> support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
Hi Maxime,
>> The exclusive rate code could support this if it doesn't already do so.
>> If you call clk_set_rate_exclusive(child, ) followed by
>> clk_set_rate(parent, ) the core code should try to keep the
>> child at the constant rate, or fail the clk_set_rate() call on the
>> parent. It should
GuC code uses in_atomic() function to determine if the current
context is atomic. As noted by the function's description it
should not be used in driver code, as it is not guaranteed to
determine atomicity correctly in every instance. This is also
pointed out by the FIXME note suggesting that the c
On Tue, 07 Jan 2025 13:58:51 +0100, Krzysztof Kozlowski wrote:
> DTS example in the bindings should be indented with 2- or 4-spaces and
> aligned with opening '- |', so correct any differences like 3-spaces or
> mixtures 2- and 4-spaces in one binding.
>
> No functional changes here, but saves s
Hi Stephen,
>> The idea is: if the flag is set, instead of accepting the new upstream
>> rate and recalculate the downstream rate based on a previously set
>> divider value, we change our divider value to match the same frequency
>> as before. But if we cannot, then we just keep the old way.
>>
>
On Fri, Jan 10, 2025 at 06:08:25PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> Add vop found on rk3576, the main difference between rk3576 and the
> previous vop is that each VP has its own interrupt line.
>
> Signed-off-by: Andy Yan
>
> ---
>
> Changes in v10:
> - Move interrupt-names back t
On Fri, Jan 10, 2025 at 9:48 AM Christian König
wrote:
>
> Am 10.01.25 um 15:32 schrieb Philipp Reisner:
> > [...]
> >> Take a look at those messages right before the crash:
> >>
> >> Jän 10 07:58:14 ryzen9 kernel: [drm] scheduler comp_1.2.1 is not ready,
> >> skipping
> >> Jän 10 07:58:14 ryzen9
Hi Sima and Dave,
Here goes one extra drm-xe-next.
The reason for this last minute and extra one towards 6.14 is
because we have 2 patches that we would like to propagate
as soon as possible to avoid later conflicts:
1. A big patch fixing typos everywhere.
2. A patch killing xe_pciids.h and adding
On Fri, Jan 10, 2025 at 5:52 AM Tvrtko Ursulin
wrote:
>
>
> On 09/01/2025 12:30, Christian König wrote:
> > Am 08.01.25 um 19:35 schrieb Tvrtko Ursulin:
> >> Lets use the existing helper instead of peeking into the structure
> >> directly.
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> Cc: Christia
Am 10.01.25 um 15:32 schrieb Philipp Reisner:
[...]
Take a look at those messages right before the crash:
Jän 10 07:58:14 ryzen9 kernel: [drm] scheduler comp_1.2.1 is not ready,
skipping
Jän 10 07:58:14 ryzen9 kernel: [drm] scheduler comp_1.3.1 is not ready,
skipping
That is basically a 100% c
Allow user to provide a low latency hint per exec queue. When set,
KMD sends a hint to GuC which results in special handling for this
exec queue. SLPC will ramp the GT frequency aggressively every time
it switches to this exec queue.
We need to enable the use of SLPC Compute strategy during init,
[...]
> Take a look at those messages right before the crash:
>
> Jän 10 07:58:14 ryzen9 kernel: [drm] scheduler comp_1.2.1 is not ready,
> skipping
> Jän 10 07:58:14 ryzen9 kernel: [drm] scheduler comp_1.3.1 is not ready,
> skipping
>
> That is basically a 100% certain confirm that an application
Add the const qualifier to all the ctl_tables in the tree except for
watchdog_hardlockup_sysctl, memory_allocation_profiling_sysctls,
loadpin_sysctl_table and the ones calling register_net_sysctl (./net,
drivers/inifiniband dirs). These are special cases as they use a
registration function with a n
On 10/01/2025 14:31, Alexandre Mergnat wrote:
> Enable the DRM HDMI connector support and the MIPI-DSI display
> Startek KD070FHFID015 panel to have HDMI and DSI display working
> on the mt8365-evk board.
>
> Reviewed-by: AngeloGioacchino Del Regno
>
> Signed-off-by: Alexandre Mergnat
> ---
Re
On 10/01/2025 06:39, Ao Xu via B4 Relay wrote:
> /* Setup PHY */
> - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1,
> meson_dw_hdmi->data->cntl1_init);
> - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0,
> meson_dw_hdmi->data->cntl0_init);
> + if (dw_hdmi_is_compatible(meson_dw_hdmi, "
spin_unlock() function enables irqs regardless of their state
before spin_lock() was called. This might result in an interrupt
while holding a lock further down in the execution, as seen in
GitLab issue #13399.
Try to remedy the problem by saving irq state before spin lock
acquisition.
Signed-off
On 10/01/2025 06:39, Ao Xu via B4 Relay wrote:
> From: Ao Xu
>
> Add devicetree document for S4 VPU
>
> Signed-off-by: Ao Xu
> ---
> .../bindings/display/amlogic,meson-vpu.yaml| 48
> --
> 1 file changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/Documenta
On Fri, 10 Jan 2025 20:34:00 +0800, paul-pl.chen wrote:
> From: "Paul-pl.Chen"
>
> Add mediatek,blender.yaml to support BLENDER for MT8196.
>
> Signed-off-by: Paul-pl.Chen
> ---
> The header used in examples:
> #include
> is not upstreamed yet.
> It will be sent by related owner soon.
> ---
On Fri, 10 Jan 2025 20:33:59 +0800, paul-pl.chen wrote:
> From: "Paul-pl.Chen"
>
> Add mediatek,exdma.yaml to support EXDMA for MT8196.
>
> Signed-off-by: Paul-pl.Chen
> ---
> The header used in examples:
> #include
> #include
> are not upstreamed yet.
> It will be sent by related owner soo
On Fri, 10 Jan 2025 20:34:01 +0800, paul-pl.chen wrote:
> From: "Paul-pl.Chen"
>
> Add mediate,outproc.yaml to support OUTPROC for MT8196.
>
> Signed-off-by: Paul-pl.Chen
> ---
> The header used in examples:
> #include
> is not upstreamed yet.
>
> It will be sent by related owner soon.
> --
On Fri 10 Jan 2025 at 13:39, Ao Xu via B4 Relay
wrote:
> From: Ao Xu
>
> Add S4 compatible for DRM driver. This update driver logic to support
> S4-specific configurations. This also add vpu clock operation in
> bind, suspend, resume, shutdown stage.
>
> Signed-off-by: Ao Xu
> ---
> drivers/g
Enable the DRM HDMI connector support and the MIPI-DSI display
Startek KD070FHFID015 panel to have HDMI and DSI display working
on the mt8365-evk board.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertion
From: Fabien Parent
DPI is part of the display / multimedia block in MediaTek SoCs, and
always have a power-domain (at least in the upstream device-trees).
Add the power-domains property to the binding example.
Fixes: 9273cf7d3942 ("dt-bindings: display: mediatek: convert the dpi bindings
to ya
The purpose of this series is to add the display support for the mt8365-evk.
This is the list of HWs / IPs support added:
- Connectors (HW):
- HDMI
- MIPI DSI (Mobile Industry Processor Interface Display Serial Interface)
- HDMI bridge (it66121)
- DSI pannel (startek,kd070fhfid015)
- SoC displ
MIPI DSI:
- Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
to power the pannel plugged to the DSI connector.
- Setup the Display Parallel Interface.
- Add the startek kd070fhfid015 pannel support.
HDMI:
- Add HDMI connector support.
- Add the "ite,it66121" HDMI bridge sup
- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
output)
- Add the display mutex support.
- Add
From: Fabien Parent
Add DRM support for MT8365 SoC.
Signed-off-by: Fabien Parent
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Alexandre Mergnat
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_d
Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered
before mtk_dsi_poweron. lanes_ready flag toggle to true during
mtk_dsi_lane_ready function, and the DSI module is set up during
mtk_dsi_poweron.
Later, during panel driver init, mtk_dsi_lane_ready is triggered but does
nothing b
On Fri, Jan 10, 2025 at 12:40:28AM +0800, Xu Yilun wrote:
> So then we face with the shared <-> private device conversion in CoCo VM,
> and in turn shared <-> private MMIO conversion. MMIO region has only one
> physical backend so it is a bit like in-place conversion which is
> complicated. I wann
Hi
Am 10.01.25 um 00:57 schrieb Dmitry Baryshkov:
On Thu, Jan 09, 2025 at 02:53:16PM +0100, Thomas Zimmermann wrote:
Hi
Am 22.12.24 um 06:00 schrieb Dmitry Baryshkov:
As pointed out by Simona, the drm_atomic_helper_check_modeset() and
drm_atomic_helper_check() require the former function is
Hi
Am 10.01.25 um 02:49 schrieb Andy Yan:
Hi Thomas,
At 2025-01-09 22:56:56, "Thomas Zimmermann" wrote:
Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
scanline pitch and allocation size. Implementations of struct
drm_driver.dumb_create can call the new helper for their size
On 09/01/2025 23:18, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:36PM +0100, Krzysztof Kozlowski wrote:
>> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
>>
>> Signed-off-by: Krzysztof Kozlowski
>> ---
>> .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 522
>> ++
On 10/01/2025 13:33, paul-pl.chen wrote:
> From: "Paul-pl.Chen"
>
> Add mediatek,exdma.yaml to support EXDMA for MT8196.
>
> Signed-off-by: Paul-pl.Chen
> ---
> The header used in examples:
> #include
> #include
> are not upstreamed yet.
Which makes this untestable and unmergeable.
This can
On Fri, 2025-01-10 at 10:47 +0100, Christian König wrote:
> Any objections that I push patch #1 and #3 to drm-misc-next?
>
> They are general cleanups anyway and this way we have them out of the
> way.
>
> Regards,
> Christian.
Please do. I have to rewrite the cover letter but that's not a big
d
On 10/01/2025 13:33, paul-pl.chen wrote:
> From: "Paul-pl.Chen"
>
> Add compatible for mmsys yaml of MT8196
>
> Signed-off-by: Paul-pl.Chen
This is a wide pattern now in Mediatek: login name is used as family
name. Repeating the same comment to every Mediatek employee is a bit
tedious, so may
On 10/01/2025 13:31, Dmitry Baryshkov wrote:
> TDA998x is the HDMI bridge driver, incorporating drm_connector and
> optional drm_encoder (created via the component bind API by the TICLDC
> and HDLCD drivers). TDA9950 is an I2C-CEC translator, being present
> on-die on the TDA9989 and TDA19989 chips
On 10/01/2025 13:31, Dmitry Baryshkov wrote:
> TDA998x is the HDMI bridge driver, incorporating drm_connector and
> optional drm_encoder (created via the component bind API by the TICLDC
> and HDLCD drivers). Thus it should be residing together with the other
> DRM bridge drivers under drivers/gpu/
On 10/01/2025 10:17, Dmitry Baryshkov wrote:
> On Fri, Jan 10, 2025 at 09:59:26AM +0100, Krzysztof Kozlowski wrote:
>> On 10/01/2025 00:18, Dmitry Baryshkov wrote:
>>> On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which
On 10/01/2025 13:31, Dmitry Baryshkov wrote:
> Move the driver for NXP TDA9950 / CEC part of TDA998x together to
> drivers/media/i2c, close to other CEC drivers. Specify 'default
> DRM_I2C_NXP_TDA998X' in order to simplify migration from old config
> files as the Kconfig name has been changed to fo
TDA998x is the HDMI bridge driver, incorporating drm_connector and
optional drm_encoder (created via the component bind API by the TICLDC
and HDLCD drivers). Thus it should be residing together with the other
DRM bridge drivers under drivers/gpu/drm/bridge/.
TDA9950 is an I2C-CEC translator, being
Move the driver for NXP TDA9950 / CEC part of TDA998x together to
drivers/media/i2c, close to other CEC drivers. Specify 'default
DRM_I2C_NXP_TDA998X' in order to simplify migration from old config
files as the Kconfig name has been changed to follow media/cec style.
Signed-off-by: Dmitry Baryshko
After the commit 0fb2970b4b6b ("drm/armada: remove non-component
support") there are no remaining users of the struct
tda998x_encoder_params. Drop the header and corresponding API from the
TDA998x driver.
Reviewed-by: Laurent Pinchart
Signed-off-by: Dmitry Baryshkov
---
MAINTAINERS
TDA998x is the HDMI bridge driver, incorporating drm_connector and
optional drm_encoder (created via the component bind API by the TICLDC
and HDLCD drivers). TDA9950 is an I2C-CEC translator, being present
on-die on the TDA9989 and TDA19989 chips.
Move TDA9950 driver to drivers/media/cec/i2c and T
drm_wait_one_vblank() uses drm_WARN() to check for a time-dependent
condition. Since syzkaller runs the kernel with the panic_on_warn set, this
causes the entire kernel to panic with a "vblank wait timed out on crtc %i"
message.
In this case it does not mean that there is something wrong with the
Add generic CEC helpers to be used by HDMI drivers. Both notifier and
and adapter are supported for registration. Once registered, the driver
can call common set of functions to update physical address, to
invalidate it or to unregister CEC data.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/d
Implement necessary glue code to let DRM bridge drivers to implement CEC
adapters support.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_bridge_connector.c | 95 ++
include/drm/drm_bridge.h | 25 +++
2 files changed, 120 inserti
Currently it is next to impossible to implement CEC handling for the
setup using drm_bridges and drm_bridge_connector: bridges don't have a
hold of the connector at the proper time to be able to route CEC events.
At the same time it not very easy and obvious to get the CEC physical
address handlin
On 10/01/2025 10:47, Alexandre Mergnat wrote:
>
>
> On 10/01/2025 08:38, Krzysztof Kozlowski wrote:
>> On 09/01/2025 11:37, Alexandre Mergnat wrote:
>>> Enable the DRM HDMI connector support.
>>> Enable the MIPI-DSI display Startek KD070FHFID015 panel.
>>
>> Why? It was in previous commit, now it
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