Hi Stephen,
Am 14.09.22 um 20:20 schrieb Stephen Boyd:
Quoting Stefan Wahren (2022-09-14 11:09:04)
Am 14.09.22 um 20:05 schrieb Stephen Boyd:
Quoting Stefan Wahren (2022-09-14 10:45:48)
Am 14.09.22 um 17:50 schrieb Stephen Boyd:
Furthermore, I wonder if even that part needs to be implemented
On Mon, 4 Jul 2022 19:11:45 +0300, Dmitry Baryshkov wrote:
> On MSM8996 the HDMI PHY is the QMP PHY, it provides an HDMI PLL clock
> used by the MMCC. Add support for providing this clock to the OF
> framework by registerding the clock provider and adding #clock-cells
> property to the DT node.
>
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2181
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2178
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/a
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2182
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2179
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/a
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2180
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../amd/display/dc/dcn321/dcn321_resource.c | 26 +--
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2177
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
.../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
On 9/14/2022 3:04 PM, Matt Roper wrote:
From: Tvrtko Ursulin
This, along with the changes already landed in commit 1c66a12ab431
("drm/i915: Handle each GT on init/release and suspend/resume") makes
engines from all GTs actually known to the driver.
To accomplish this we need to sprinkle a l
Hi Maíra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip linus/master
v6.0-rc5 next-20220914]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree
On 9/14/2022 4:46 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms tha
On 9/12/2022 6:09 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A patch was merged to remove the GuC log size override module
parameters. That patch was broken and caused kernel error messages on
boot in non CONFIG_DEBUG_GUC|GEM builds:
[ 12.085121] i915 :00:02.0: [drm] *ERR
(Hardware) resources which are bound to the driver and device lifecycle
must not be accessed after the device and driver are unbound.
However, the DRM device isn't freed as long as the last user didn't
close it, hence userspace can still call into the driver.
Therefore protect the critical sectio
Remove the trailing return statements at the end of void functions.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 1 -
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
Use drm managed resource allocation (drmm_universal_plane_alloc()) in
order to get rid of the explicit destroy hook in struct drm_plane_funcs.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4 ++--
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 25 -
Use drmm_crtc_init_with_planes() instead of drm_crtc_init_with_planes()
to get rid of the explicit destroy hook in struct drm_plane_funcs.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drive
(Hardware) resources which are bound to the driver and device lifecycle
must not be accessed after the device and driver are unbound.
However, the DRM device isn't freed as long as the last user didn't
close it, hence userspace can still call into the driver.
Therefore protect the critical sectio
When the driver is unbound, there might still be users in userspace
having an open fd and are calling into the driver.
While this is fine for drm managed resources, it is not for resources
bound to the device/driver lifecycle, e.g. clocks or MMIO mappings.
To prevent use-after-free issues we need
Use drm managed resources to allocate driver structures and get rid of
the deprecated drm_dev_alloc() call and replace it with
devm_drm_dev_alloc().
This also serves as preparation to get rid of drm_device->dev_private
and to fix use-after-free issues on driver unload.
Signed-off-by: Danilo Krumm
Using drm_device->dev_private is deprecated. Since we've switched to
devm_drm_dev_alloc(), struct drm_device is now embedded in struct
malidp_drm, hence we can use container_of() to get the struct drm_device
instance instead.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_dr
Hi,
This patch series converts the driver to use drm managed resources to prevent
potential use-after-free issues on driver unbind/rebind and to get rid of the
usage of deprecated APIs.
Danilo Krummrich (8):
drm/fsl-dcu: use drmm_* to allocate driver structures
drm/fsl-dcu: replace drm->dev_p
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms that are officially GuC/HuC enabled.
Also, update the expected
From: John Harrison
Update the GuC version numbers to expect the latest release. Also
start using GuC/HuC firmware files with reduced version information in
the file name.
Signed-off-by: John Harrison
John Harrison (1):
drm/i915/uc: Update to latest GuC and use new-format GuC/HuC names
dr
From: Tvrtko Ursulin
This, along with the changes already landed in commit 1c66a12ab431
("drm/i915: Handle each GT on init/release and suspend/resume") makes
engines from all GTs actually known to the driver.
To accomplish this we need to sprinkle a lot of for_each_gt calls around
but is otherwi
From: Tvrtko Ursulin
Walk all GTs from i915_gem_resume when resuming engines.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/
Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0. Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.
From: Tvrtko Ursulin
Walk all GTs when suspending.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/
From: Chris Wilson
If we abort driver initialisation in the middle of gt/engine discovery,
some engines will be fully setup and some not. Those incompletely setup
engines only have 'engine->release == NULL' and so will leak any of the
common objects allocated.
Signed-off-by: Chris Wilson
Cc: Ja
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2
On 14/09/2022 20:23, Jason-JH.Lin wrote:
The compatible properties of mt8195 have changed to mediatek,mt8195-vdosys0
and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove the unused
compatible.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC
binding")
Signe
On 14/09/2022 20:23, Jason-JH.Lin wrote:
In mt8195, vdosys0 and vdosys1 are 2 different function blocks
for mediatek-drm, so using 2 compatible instead of identifying
multiple mmsys by io_start.
Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for mt8195 vdosys0")
Signed-off-by: Jas
On 2022-09-14 10:55, Michel Dänzer wrote:
[ Adding the dri-devel list ]
On 2022-09-14 18:30, Alex Hung wrote:
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors w
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f117c01187301a087412bd6697fcf5463cb427d8 Add linux-next specific
files for 20220914
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209150141.wgbakqmx-...@intel.com
https
Hi Dave, Daniel,
Fixes for 6.0. A bit bigger than usual, but this is mainly caused by some
regression fixes which took a while to sort out and validate. The rest is
fixes for new IPs added in the 6.0 cycle.
The following changes since commit 2edb79a5fb303dff577d6a0c7d571c3bab1d1455:
Merge ta
Am 14.09.22 um 20:14 schrieb Stephen Boyd:
Quoting Stefan Wahren (2022-09-14 11:09:04)
Am 14.09.22 um 20:05 schrieb Stephen Boyd:
Quoting Stefan Wahren (2022-09-14 10:45:48)
Am 14.09.22 um 17:50 schrieb Stephen Boyd:
Furthermore, I wonder if even that part needs to be implemented. Why
not ma
Quoting Stefan Wahren (2022-09-14 11:09:04)
> Am 14.09.22 um 20:05 schrieb Stephen Boyd:
> > Quoting Stefan Wahren (2022-09-14 10:45:48)
> >> Am 14.09.22 um 17:50 schrieb Stephen Boyd:
> >>> Furthermore, I wonder if even that part needs to be implemented. Why
> >>> not make a direct call to rpi_fi
Quoting Stefan Wahren (2022-09-14 11:09:04)
> Am 14.09.22 um 20:05 schrieb Stephen Boyd:
> > Quoting Stefan Wahren (2022-09-14 10:45:48)
> >> Am 14.09.22 um 17:50 schrieb Stephen Boyd:
> >>> Furthermore, I wonder if even that part needs to be implemented. Why
> >>> not make a direct call to rpi_fi
On Wed, Sep 14, 2022 at 04:51:03PM +, Winkler, Tomas wrote:
> >
> > On DG2, HuC loading is performed by the GSC, via a PXP command. The load
> > operation itself is relatively simple (just send a message to the GSC with
> > the
> > physical address of the HuC in LMEM), but there are timing ch
Am 14.09.22 um 20:05 schrieb Stephen Boyd:
Quoting Stefan Wahren (2022-09-14 10:45:48)
Am 14.09.22 um 17:50 schrieb Stephen Boyd:
Furthermore, I wonder if even that part needs to be implemented. Why
not make a direct call to rpi_firmware_property() and get the max rate?
All of that can live in
Quoting Maxime Ripard (2022-09-14 09:15:02)
> Hi Stephen,
>
> Thanks for reviewing that series
>
> On Wed, Sep 14, 2022 at 08:50:33AM -0700, Stephen Boyd wrote:
> > Quoting Maxime Ripard (2022-08-15 08:31:24)
> > > @@ -254,6 +255,33 @@ static int raspberrypi_fw_dumb_determine_rate(struct
> > > c
Quoting Stefan Wahren (2022-09-14 10:45:48)
> Am 14.09.22 um 17:50 schrieb Stephen Boyd:
> >
> > Furthermore, I wonder if even that part needs to be implemented. Why
> > not make a direct call to rpi_firmware_property() and get the max rate?
> > All of that can live in the drm driver. Making it a
Hi,
Am 14.09.22 um 17:50 schrieb Stephen Boyd:
Quoting Maxime Ripard (2022-08-15 08:31:24)
@@ -254,6 +255,33 @@ static int raspberrypi_fw_dumb_determine_rate(struct
clk_hw *hw,
return 0;
}
+unsigned long rpi_firmware_clk_get_max_rate(struct clk *clk)
+{
+ const struct rasp
On 9/13/2022 5:58 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a b
There is a spelling mistake in a pr_debug message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 752
Hi,
On 9/14/22 12:29, Maxime Ripard wrote:
> Hi Hans,
>
> On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
>> Hi All,
>>
>> Now that all patches have been reviewed/acked here is an immutable
>> backlight-detect-refactor
>> branch with 6.0-rc1 + the v5 patch-set, for merging into th
>
> On DG2, HuC loading is performed by the GSC, via a PXP command. The load
> operation itself is relatively simple (just send a message to the GSC with the
> physical address of the HuC in LMEM), but there are timing changes that
> requires special attention. In particular, to send a PXP command
Using the parent fence instead of the finished fence
to get the job status. This change is to avoid GPU
scheduler timeout error which can cause GPU reset.
Signed-off-by: Arvind Yadav
Reviewed-by: Andrey Grodzovsky
---
changes in v1,v2 - Enable signaling for finished fence in sche_main()
is remo
Fence signaling must be enabled to make sure that
the dma_fence_is_signaled() function ever returns true.
Since drivers and implementations sometimes mess this up,
this ensures correct behaviour when DMABUF_DEBUG_ENABLE_SIGNALING
is used during debugging.
This should make any implementation bugs re
Here's enabling software signaling on fence for selftest.
Signed-off-by: Arvind Yadav
Reviewed-by: Christian König
---
Changes in v1 :
1- Addressing Christian's comment to remove unnecessary callback.
2- Replacing CONFIG_DEBUG_WW_MUTEX_SLOWPATH instead of CONFIG_DEBUG_FS.
3- The version of this
dma_fence_wait() should always enable signaling even
when the fence is already signaled.
Signed-off-by: Arvind Yadav
---
Changes in v1..v3: This new patch was not part of previous series.
---
drivers/dma-buf/dma-fence.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/
Here's setting software signaling bit for the stub fence
which is always signaled. If this fence signaling bit is
not set then the AMD GPU scheduler will cause a GPU reset
due to a GPU scheduler cleanup activity timeout.
Signed-off-by: Arvind Yadav
Reviewed-by: Christian König
---
Changes in v1
Remove the signaled bit status check because it is returning
early when the fence is already signaled and
__dma_fence_enable_signaling is checking the status of signaled
bit again.
Signed-off-by: Arvind Yadav
Reviewed-by: Christian König
---
Changes in v1, v2: This new patch was not part of pre
Fence signaling must be enabled to make sure that
the dma_fence_is_signaled() function ever returns true.
Since drivers and implementations sometimes mess this up,
this ensures correct behaviour when DEBUG_WW_MUTEX_SLOWPATH
is used during debugging.
This should make any implementation bugs resultin
On 9/13/2022 17:58, john.c.harri...@intel.com wrote:
From: John Harrison
The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a backup
From: John Harrison
Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms that are officially GuC/HuC enabled.
Also, update the expected
From: John Harrison
Start using GuC/HuC firmware files with reduced version information in
the file name.
Signed-off-by: John Harrison
John Harrison (1):
drm/i915/uc: Enable version reduced firmware files for newest
platforms
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 12 +++-
Hi,
> Hi
>
> Am 14.09.22 um 16:58 schrieb Wang Yugui:
> > Hi,
> >
> >> (cc: Jocelyn)
> >>
> >> Hi
> >>
> >> Am 14.09.22 um 10:29 schrieb Wang Yugui:
> >>> Hi,
> >>>
> >>>
> Hi
>
> Am 13.09.22 um 17:15 schrieb Wang Yugui:
> [...]
> >>>
> >>> so I tried to revert patch
Hi Stephen,
Thanks for reviewing that series
On Wed, Sep 14, 2022 at 08:50:33AM -0700, Stephen Boyd wrote:
> Quoting Maxime Ripard (2022-08-15 08:31:24)
> > @@ -254,6 +255,33 @@ static int raspberrypi_fw_dumb_determine_rate(struct
> > clk_hw *hw,
> > return 0;
> > }
> >
> > +unsigned
On Wed, Sep 07, 2022 at 09:23:01AM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 05.09.22 um 18:32 schrieb Thierry Reding:
> > From: Thierry Reding
> >
> > Add a conversion helper for the AB24 format to use in drm_fb_blit().
> >
> > Signed-off-by: Thierry Reding
> > ---
> > drivers/gpu/drm/drm
On Tue, Sep 06, 2022 at 09:27:21AM -0500, Rob Herring wrote:
> On Mon, Sep 05, 2022 at 06:32:56PM +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Document the "framebuffer" compatible string for reserved memory nodes
> > to annotate reserved memory regions used for framebuffer carve
Quoting Maxime Ripard (2022-08-15 08:31:24)
> @@ -254,6 +255,33 @@ static int raspberrypi_fw_dumb_determine_rate(struct
> clk_hw *hw,
> return 0;
> }
>
> +unsigned long rpi_firmware_clk_get_max_rate(struct clk *clk)
> +{
> + const struct raspberrypi_clk_data *data;
> + struc
Hi
Am 14.09.22 um 16:58 schrieb Wang Yugui:
Hi,
(cc: Jocelyn)
Hi
Am 14.09.22 um 10:29 schrieb Wang Yugui:
Hi,
Hi
Am 13.09.22 um 17:15 schrieb Wang Yugui:
[...]
so I tried to revert patch of mgag200 driver in batch of 2 or 3, the I
noticed the patch 'Subject: drm/mgag200: Remove specia
On Wed, Sep 14, 2022 at 9:32 AM Thierry Reding wrote:
>
> On Wed, Sep 14, 2022 at 03:19:01PM +0300, Mikko Perttunen wrote:
> > On 9/14/22 15:08, Rob Herring wrote:
> > > On Tue, Sep 13, 2022 at 04:14:41PM +0300, Mikko Perttunen wrote:
> > > > From: Mikko Perttunen
> > > >
> > > > Update NVDEC bin
Hi,
> (cc: Jocelyn)
>
> Hi
>
> Am 14.09.22 um 10:29 schrieb Wang Yugui:
> > Hi,
> >
> >
> >> Hi
> >>
> >> Am 13.09.22 um 17:15 schrieb Wang Yugui:
> >> [...]
> >
> > so I tried to revert patch of mgag200 driver in batch of 2 or 3, the I
> > noticed the patch 'Subject: drm/mgag200: Re
Fix addressing in the NXP TDA998x HDMI transmitters' subnodes:
- Add missing #{address,size}-cells properties to ports capsule,
- Add missing reg properties to port child nodes,
- Drop bogus unit addresses from endpoint grandchildren nodes.
Signed-off-by: Geert Uytterhoeven
---
v2:
- No c
Convert the NXP TDA998x HDMI transmitter Device Tree binding
documentation to json-schema.
Add missing "#sound-dai-cells" property.
Add ports hierarchy, as an alternative to port.
Drop pinctrl properties, as they do not belong here.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Add maximum to vi
Hi all,
This patch series converts the NXP TDA998x HDMI transmitter Device Tree
binding documentation to json-schema, after a few customary fixes.
Changes compared to v1:
- Add maximum to video-ports,
- Drop unneeded maxItems for audio-ports,
- Complete port descriptions.
Thanks fo
The NXP TDA998x HDMI transmitter Device Tree binding documentation does
not mention a clocks property.
Signed-off-by: Geert Uytterhoeven
---
Is this property just missing from the bindings?
The driver doesn't seem to use it.
v2:
- No changes.
---
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dt
(cc: Jocelyn)
Hi
Am 14.09.22 um 10:29 schrieb Wang Yugui:
Hi,
Hi
Am 13.09.22 um 17:15 schrieb Wang Yugui:
[...]
so I tried to revert patch of mgag200 driver in batch of 2 or 3, the I
noticed the patch 'Subject: drm/mgag200: Remove special case for G200SE
with <2 MiB' and then tried this d
On Wed, Sep 14, 2022 at 03:19:01PM +0300, Mikko Perttunen wrote:
> On 9/14/22 15:08, Rob Herring wrote:
> > On Tue, Sep 13, 2022 at 04:14:41PM +0300, Mikko Perttunen wrote:
> > > From: Mikko Perttunen
> > >
> > > Update NVDEC bindings for Tegra234. This new engine version only has
> > > two memor
On 2022-09-14 06:36, Anup K Parikh wrote:
Fix two warnings during doc build which also results in corresponding
additions in generated docs
Warnings Fixed:
1. include/drm/gpu_scheduler.h:462: warning: Function parameter or member
'dev' not described in 'drm_gpu_scheduler'
2. drivers/gpu/dr
Applied. Thanks!
On Wed, Sep 14, 2022 at 3:53 AM Yihao Han wrote:
>
> ./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68:
> WARNING: conversion to bool not needed here
>
> Generated by: scripts/coccinelle/misc/boolconv.cocci
> Signed-off-by: Yihao Han
> ---
> drivers/gpu/drm/amd/disp
Applied the series. Thanks!
Alex
On Wed, Sep 14, 2022 at 1:29 AM Jiapeng Chong
wrote:
>
> These three functions are not used outside the function
> dcn32_optc.c, so the modification is defined as static.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning:
> no previ
On 13.09.2022 22:55, Nathan Huckleberry wrote:
All of the functions used for intel_dvo_dev_ops.mode_valid have a return
type of enum drm_mode_status, but the mode_valid field in the struct
definition has a return type of int.
The mismatched return type breaks forward edge kCFI since the underlyi
On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote:
> On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote:
> > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote:
> > > Hi,
> > >
> > > On 9/12/22 20:02, Chris Morgan wrote:
> > > > From: Chris Morgan
> > >
> > > Cc:
On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote:
> On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote:
> > Hi,
> >
> > On 9/12/22 20:02, Chris Morgan wrote:
> > > From: Chris Morgan
> >
> > Cc: Sascha -> any thoughts on this one?
> >
> > Best regards,
> > Michael
> >
>
On 9/14/22 15:08, Rob Herring wrote:
On Tue, Sep 13, 2022 at 04:14:41PM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware f
Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.
Representation: master_flush && (PCC_flush | IGC_flush .. etc )
This change adds necessary support for the above design.
Changes in v1:
- Few nit
On Tue, Sep 13, 2022 at 04:14:41PM +0300, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> Update NVDEC bindings for Tegra234. This new engine version only has
> two memory clients, but now requires three clocks, and as a bigger
> change the engine loads firmware from a secure carveout configur
Hi Hans,
On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
> Hi All,
>
> Now that all patches have been reviewed/acked here is an immutable
> backlight-detect-refactor
> branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi,
> drm-* and pdx86)
> subsystems.
>
On Tue, 13 Sep 2022, Stanislav Lisovskiy wrote:
> Adding DP DSC register definitions, we might need for further
> DSC implementation, supporting MST and DP branch pass-through mode.
>
> v2: - Fixed checkpatch comment warning
> v3: - Removed function which is not yet used(Jani Nikula)
>
> Reviewed-
The function dac_read_reg() is defined in the arkfb.c file, but not
called elsewhere, so delete this unused function.
drivers/video/fbdev/arkfb.c:322:18: warning: unused function 'dac_read_reg'.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2155
Reported-by: Abaci Robot
Signed-off-by: Jia
The function shadowmode_off() is defined in the tridentfb.c file, but not
called elsewhere, so delete this unused function.
drivers/video/fbdev/tridentfb.c:1131:20: warning: unused function
'shadowmode_off'.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2154
Reported-by: Abaci Robot
Sign
The function VAR_MATCH is defined in the controlfb.c file, but not
called elsewhere, so delete this unused function.
drivers/video/fbdev/controlfb.c:111:19: warning: unused function 'VAR_MATCH'.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2153
Reported-by: Abaci Robot
Signed-off-by: Jia
Thanks Jani for the review and suggestions.
I agree with the suggestions and will make changes in next version.
Please find my response inline:
On 9/13/2022 7:24 PM, Jani Nikula wrote:
On Thu, 11 Aug 2022, Ankit Nautiyal wrote:
Replace multiple log lines with a single log line at the end of
Hi Dave,
On Fri, Mar 4, 2022 at 8:48 PM Dave Stevenson
wrote:
>
> DSI sink devices typically want the DSI host powered up and configured
> before they are powered up. pre_enable is the place this would normally
> happen, but they are called in reverse order from panel/connector towards
> the enco
On Wed, Sep 14, 2022 at 2:51 PM Marek Szyprowski
wrote:
>
> Hi Jagan,
>
> On 13.09.2022 19:29, Jagan Teki wrote:
> > On Wed, Sep 7, 2022 at 3:34 PM Marek Szyprowski
> > wrote:
> >> On 06.09.2022 21:07, Jagan Teki wrote:
> >>> On Mon, Sep 5, 2022 at 4:54 PM Marek Szyprowski
> >>> wrote:
> On
On Tue, 13 Sep 2022 13:55:55 -0700, Nathan Huckleberry wrote:
> The mode_valid field in drm_connector_helper_funcs is expected to be of
> type:
> enum drm_mode_status (* mode_valid) (struct drm_connector *connector,
>struct drm_display_mode *mode);
>
> The misma
Hi Jagan,
On 13.09.2022 19:29, Jagan Teki wrote:
> On Wed, Sep 7, 2022 at 3:34 PM Marek Szyprowski
> wrote:
>> On 06.09.2022 21:07, Jagan Teki wrote:
>>> On Mon, Sep 5, 2022 at 4:54 PM Marek Szyprowski
>>> wrote:
On 02.09.2022 12:47, Marek Szyprowski wrote:
> On 29.08.2022 20:40, Jagan
From: Yihao Han
[ Upstream commit 5491424d17bdeb7b7852a59367858251783f8398 ]
clk_put() already checks the clk ptr using !clk and IS_ERR()
so there is no need to check it again before calling it.
Signed-off-by: Yihao Han
Reviewed-by: Hans de Goede
Signed-off-by: Helge Deller
Signed-off-by: Sa
From: Hyunwoo Kim
[ Upstream commit a09d2d00af53b43c6f11e6ab3cb58443c2cac8a7 ]
In pxa3xx_gcu_write, a count parameter of type size_t is passed to words of
type int. Then, copy_from_user() may cause a heap overflow because it is used
as the third argument of copy_from_user().
Signed-off-by: Hyu
From: Petr Cvek
[ Upstream commit 25c9a15fb7bbfafb94dd3b4e3165c18b8e1bd039 ]
Aperture size for i9x5 variants is determined from PCI base address.
if (pci_resource_start(pdev, 2) & 0x0800)
*aperture_size = MB(128);
...
This condition is incorrect as 128 MiB a
From: Xiang wangx
[ Upstream commit fc378794a2f7a19cf26010dc33b89ba608d4c70f ]
Delete the redundant word 'its'.
Signed-off-by: Xiang wangx
Signed-off-by: Helge Deller
Signed-off-by: Sasha Levin
---
drivers/video/fbdev/skeletonfb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Maxime Ripard
[ Upstream commit 2523e9dcc3be91bf9fdc0d1e542557ca00bbef42 ]
We'll need to extend the vc4_async_flip_state structure to rely on
another callback implementation, so let's move the current one into a
union.
Reviewed-by: Melissa Wen
Signed-off-by: Maxime Ripard
Link: https://
From: Clément Péron
[ Upstream commit d76034a427a2660b080bc155e4fd8f6393eefb48 ]
Enabling panfrost GPU OPP with dynamic regulator will make OPP
responsible to enable and configure it.
Unfortunately OPP configure and enable the regulator when an OPP
is asked to be set, which is not the case duri
From: Clément Péron
[ Upstream commit d76034a427a2660b080bc155e4fd8f6393eefb48 ]
Enabling panfrost GPU OPP with dynamic regulator will make OPP
responsible to enable and configure it.
Unfortunately OPP configure and enable the regulator when an OPP
is asked to be set, which is not the case duri
From: Guchun Chen
[ Upstream commit aac4cec1ec45d72bd03eaf3fd772c5a609f5ed26 ]
It's missed in psp fini.
Signed-off-by: Guchun Chen
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +--
1 file changed, 5 ins
From: ZhenGuo Yin
[ Upstream commit d91c411c744b55e860fbafc9a499f4f22d64c762 ]
[Why]
Ghost BO is released with non-empty bulk move object. There is a
warning trace:
WARNING: CPU: 19 PID: 1582 at ttm/ttm_bo.c:366 ttm_bo_release+0x2e1/0x2f0
[amdttm]
Call Trace:
amddma_resv_reserve_fences+0x10d/
Hi,
> Hi
>
> Am 13.09.22 um 17:15 schrieb Wang Yugui:
> [...]
> >>>
> >>> so I tried to revert patch of mgag200 driver in batch of 2 or 3, the I
> >>> noticed the patch 'Subject: drm/mgag200: Remove special case for G200SE
> >>> with <2 MiB' and then tried this dirty fix.
> >>
> >> Oh, great wor
On Tue, Aug 30, 2022 at 1:12 AM Adam Ford wrote:
>
> On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki wrote:
> >
> > The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
> > with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
> > range from BIT[18-13] and th
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