Am 27.04.22 um 18:03 schrieb Daniel Vetter:
On Thu, Apr 21, 2022 at 09:10:02PM +0200, Christian König wrote:
drm_gem_plane_helper_prepare_fb() was using
drm_atomic_set_fence_for_plane() which ignores all implicit fences when an
explicit fence is already set. That's rather unfortunate when the fb
Hi Maxime,
On 27.04.2022 16:34, Maxime Ripard wrote:
> On Tue, Apr 26, 2022 at 01:40:31PM +0530, Jagan Teki wrote:
>> On Tue, Apr 26, 2022 at 1:24 PM Paul Kocialkowski
>> wrote:
>>> On Thu 21 Apr 22, 10:59, Paul Kocialkowski wrote:
On Thu 21 Apr 22, 10:23, Maxime Ripard wrote:
> On Thu,
Hi Dave & Daniel,
Here goes drm-intel-fixes PR for v5.18-rc5.
Fixes for backlight control on XMG Core 15 e21 (#5284, regression since
5.15) and black display plane on Acer One AO532h.
Then two smaller display fixes picked up by tooling.
Regards, Joonas
***
drm-intel-fixes-2022-04-28:
- Fix #5
++Laurent ,Dmitry, Abhinav and Rob
> Adding support for writeback transcoder to start capturing frames using
> interrupt mechanism
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> drivers/gp
++Laurent ,Dmitry, Abhinav and Rob
> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, April 21, 2022 10:38 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com;
> Murthy, Arun R ; Kandpal, Suraj
>
> Subjec
On Wed, Apr 27, 2022 at 03:14:16PM -0700, John Harrison wrote:
On 4/27/2022 11:24, Timo Aaltonen wrote:
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this se
++Laurent ,Dmitry, and Abhinav
Hi,
Can you have a look at the private implementation i915 is currently going with
till
we can figure out how to work with drm core .
Regards,
Suraj Kandpal
> A patch series was floated in the drm mailing list which aimed to change the
> drm_connector and drm_enco
We're now ready to start exposing compute engines to userspace.
v2:
- Move kerneldoc for other engine classes to a separate patch. (Andi)
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Cc: Jordan Justen
Cc: Szymon Morek
UMD (mesa): https://gitlab.freedesktop.org/mesa/me
Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the ua
From: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
Compute engines have a separate register that the driver should use to
perform MMIO-based TLB invalidation.
Note that the term "context" in this register's bspec description is
used to refer to the engine instance (in the same way "context" is used
on bspec 46167).
Bspec: 43930
Cc: Prathap Kumar
We'll be adding a new type of engine soon. Let's document the existing
engine classes first to help make it clear what each type of engine is
used for.
Cc: Andi Shyti
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 53 -
1 file changed, 47 insert
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Dan
Hi Dave, Daniel,
Fixes for 5.18.
The following changes since commit b2d229d4ddb17db541098b83524d901257e93845:
Linux 5.18-rc3 (2022-04-17 13:57:31 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.18-2022-04-27
for you to fe
Hi Laurent,
Thank you for your comment.
We had never imagined that affine driver can be a V4L2 driver.
Affine is one of the accelerators in Visconti, and some accelerators
receive/yield non-picture data.
Also, as the original accelerator drivers were implemented for kernel 4.19.x,
we were not a
On 4/27/22 04:43, Pekka Paalanen wrote:
On Tue, 26 Apr 2022 22:22:22 -0300
Igor Torrente wrote:
On April 26, 2022 10:03:09 PM GMT-03:00, Igor Torrente
wrote:
On 4/25/22 22:54, Igor Torrente wrote:
Hi Pekka,
On 4/25/22 05:10, Pekka Paalanen wrote:
On Sat, 23 Apr 2022 15:53:20 -0300
I
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Dan
On 4/27/2022 9:55 AM, john.c.harri...@intel.com wrote:
From: John Harrison
First release of GuC for DG2.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 85
1 file changed, 4
Rather than storing subslice masks internally as u8[] (inside the sseu
structure) and u32 (everywhere else), let's move over to using an
intel_sseu_ss_mask_t typedef compatible with the operations in
linux/bitmap.h. We're soon going to start adding code for a new
platform where subslice masks are
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated. Given that modern
platforms (gen11 and beyond) are architecturally guaranteed to have
equivalent EU masks fo
This series makes a handful of updates to i915's internal handling of
slice/subslice/EU (SSEU) data to handle recent platforms like Xe_HP in a
more natural manner and to prepare for some additional upcoming
platforms we have in the pipeline (the first of which I'll probably
start sending patches fo
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditio
Fix the following -Wstringop-overflow warnings when building with GCC-11:
drivers/gpu/drm/i915/intel_pm.c:3106:9: warning: ‘intel_read_wm_latency’
accessing 16 bytes in a region of size 10 [-Wstringop-overflow=]
3106 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
|
The DRM_DP_AUX_CHARDEV and DRM_DP_CEC Kconfig symbols enable code that use
DP helper functions, that are only present if CONFIG_DRM_DISPLAY_DP_HELPER
is also enabled.
But these don't select the DRM_DISPLAY_DP_HELPER symbol, meaning that it
is possible to enable any of them without CONFIG_DRM_DISPL
On 4/27/2022 11:24, Timo Aaltonen wrote:
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new versio
Hi Yuji,
Thank you for the patch. It's nice to see contributions from Toshiba in
the image acceleration domain :-)
I'll start with a high-level question before diving into detailed
review. Why is this implemented in drivers/soc/ with a custom userspace
API, and not as a V4L2 memory-to-memory driv
On 4/27/22 22:25, Javier Martinez Canillas wrote:
> The DRM_DP_AUX_CHARDEV and DRM_DP_CEC boolean Kconfig symbols enable code
> that use DP helper functions, exported by the display-helper module.
>
[snip]
> @@ -32,6 +32,8 @@ config DRM_DISPLAY_HDMI_HELPER
> config DRM_DP_AUX_CHARDEV
> bo
On Wed, Apr 27, 2022 at 5:41 PM Harry Wentland wrote:
>
>
>
> On 2022-04-27 06:52, Pekka Paalanen wrote:
> > Hi Ville and Alex,
> >
> > thanks for the replies. More below.
> >
> > TL;DR:
> >
> > My take-away from this is that I should slam 'max bpc' to the max by
> > default, and offer a knob for
Tested-by: Kuogee Hsieh
On 4/26/2022 2:17 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 2:11 PM Abhinav Kumar wrote:
On 4/26/2022 1:26 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 12:20 PM Abhinav Kumar
wrote:
Missed one more comment.
On 4/26/2022 12:16 PM, Abhinav Kuma
Tested-by: Kuogee Hsieh
On 4/26/2022 2:21 PM, Abhinav Kumar wrote:
On 4/26/2022 1:52 PM, Doug Anderson wrote:
Hi,
On Tue, Apr 26, 2022 at 1:46 PM Abhinav Kumar
wrote:
On 4/26/2022 1:21 PM, Douglas Anderson wrote:
If we're unable to read the EDID for a display because it's corrupt /
bo
On 4/26/2022 5:26 PM, Daniele Ceraolo Spurio wrote:
The huc_is_authenticated function return is based on our SW tracking of
the HuC auth status. However, around suspend/resume and reset this can
go out of sync with the actual HW state, which is why we use
huc_check_state() to look at the actua
The DRM_DP_AUX_CHARDEV and DRM_DP_CEC boolean Kconfig symbols enable code
that use DP helper functions, exported by the display-helper module.
But these don't select the DRM_DISPLAY_DP_HELPER and DRM_DISPLAY_HELPER
symbols, to make sure that the functions used will be present. This leads
to the fo
This patch enables and exposes to the nested guest
the support for the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 099329711ad13..431281ccc40ef 100644
--- a/a
By default, peers of a vCPU, can send it doorbell messages,
only when that vCPU is assigned (loaded) a physical CPU.
However when doorbell messages are not allowed, this causes all of
the vCPU's peers to get VM exits, which is suboptimal when this
vCPU is not halted, and therefore just temporary n
This patch implements the doorbell msr emulation
for nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 49 +
arch/x86/kvm/svm/svm.c | 2 ++
arch/x86/kvm/svm/svm.h | 1 +
3 files changed, 52 insertions(+)
diff --git a/arch/x86/kv
* SVM_EXIT_AVIC_UNACCELERATED_ACCESS is always forwarded to the L1
* SVM_EXIT_AVIC_INCOMPLETE_IPI is hidden from the guest if:
- is_running was false in shadow physid page because L1's vCPU
was scheduled out - in this case, the vCPU is waken up,
and it will process nested AVIC on nex
An AVIC table invalidation is not supposed to happen often, and can
only happen when the guest does something suspicious such as:
- It places physid page in a memslot that is enabled/disabled and memslot
flushing happens.
- It tries to update apic backing page addresses - guest has no
This will be used on SVM to reload shadow page of the AVIC physid table
No functional change intended
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm-x86-ops.h | 2 +-
arch/x86/include/asm/kvm_host.h| 3 +--
arch/x86/kvm/vmx/vmx.c | 8
arch/x86/kvm/x86.c
* Passthrough guest's avic pages that can be passed through
- logical id table
- avic backing page
* Passthrough AVIC's mmio range
- nested guest is responsible for marking it RW
in its NPT tables.
* Write track physical id page
- all peer's avic backing pages are
For each vCPU
- store a linked list of all shadow physical id entries
which address it.
- Update those entries when this vCPU is scheduled
in/out
- update this list, when physid tables are modified by
other means (guest write and/or table sync)
To avoid races vs vcpu schedule,
Implement the shadow physical id table and its
write tracking code which will be soon used for the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 461 +++-
arch/x86/kvm/svm/svm.h | 71 +++
2 files changed, 524 insertions(+), 8 d
This implements a few helpers that help manipulate the AVIC's
physical and logical id table entries.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/svm.h | 45 ++
1 file changed, 45 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/
This patch adds few tracepoints that will be used
to debug/profile the nested AVIC.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/trace.h | 157 ++-
arch/x86/kvm/x86.c | 13
2 files changed, 169 insertions(+), 1 deletion(-)
diff --git a/arch/x86/
This will make the code a bit easier to read when nested AVIC support
is added.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 51 +++--
arch/x86/kvm/svm/svm.h | 14 ++-
2 files changed, 37 insertions(+), 2
If a non leaf mmu page is write tracked externally for some reason,
which can in theory happen if it was used for nested avic physid page
before, then this code will enter an endless loop of page faults because
unprotecting the mmu page will not remove write tracking, nor will the
write tracker cal
This is a tiny refactoring, and can be useful to check
if a GPA/GFN is within a memslot a bit more cleanly.
Signed-off-by: Maxim Levitsky
---
include/linux/kvm_host.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
This will be used to enable write tracking from nested AVIC code
and can also be used to enable write tracking in GVT-g module
when it actually uses it as opposed to always enabling it,
when the module is compiled in the kernel.
No functional change intended.
Signed-off-by: Maxim Levitsky
---
a
This allows to enable the write tracking only when KVMGT is
actually used and doesn't carry any penalty otherwise.
Tested by booting a VM with a kvmgt mdev device.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/Kconfig | 3 ---
arch/x86/kvm/mmu/mmu.c | 2 +-
drivers/gpu/dr
AVIC is now inhibited if the guest changes apic id, thus remove
that broken code.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/svm/avic.c | 35 ---
1 file changed, 35 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 54fe03714f8a
Neither of these settings should be changed by the guest and it is
a burden to support it in the acceleration code, so just inhibit
it instead.
Also add a boolean 'apic_id_changed' to indicate if apic id ever changed.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 3 +++
a
These days there are too many AVIC/APICv inhibit
reasons, and it doesn't hurt to have some documentation
for them.
Signed-off-by: Maxim Levitsky
---
arch/x86/include/asm/kvm_host.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/inc
This is V3 of my nested AVIC patches.
I fixed few more bugs, and I also split the cod insto smaller patches.
Review is welcome!
Best regards,
Maxim Levitsky
Maxim Levitsky (19):
KVM: x86: document AVIC/APICv inhibit reasons
KVM: x86: inhibit APICv/AVIC when the guest and/or host cha
On Wed, Apr 27, 2022 at 12:25:27PM +0100, Andre Przywara wrote:
> The Arm Mali Display Processor (DP) 5xx/6xx is a series of IP that scans
> out a framebuffer and hands the pixels over to a digital signal encoder.
> It supports multiple layers, scaling and rotation.
>
> Convert the existing DT bin
On Wed, Apr 27, 2022 at 12:25:26PM +0100, Andre Przywara wrote:
> The Arm HDLCD is a display controller that scans out a framebuffer and
> hands a signal to a digital encoder to generate a DVI or HDMI signal.
>
> Convert the existing DT binding to DT schema.
>
> Signed-off-by: Andre Przywara
> -
On 25/04/2022 17:24, Ramalingam C wrote:
While locating the start of ccs scatterlist in smem scatterlist, that has
to be the size of lmem obj size + corresponding ccs data size. Report bug
if scatterlist terminate before that length.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/int
On 25/04/2022 17:24, Ramalingam C wrote:
Calculate the ccs_sz that needs to be emitted based on the src
and dst pages emitted per chunk. And handle the return value of emit_pte
for the ccs pages.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 36 +---
On 4/27/22 15:47, Saurabh Sengar wrote:
> This patch fixes a bug where GEN1 VMs doesn't allow resolutions greater
> than 64 MB size (eg 7680x4320). Unnecessary PCI check limits Gen1 VRAM
> to legacy PCI BAR size only (ie 64MB). Thus any, resolution requesting
> greater then 64MB (eg 7680x4320) woul
Hi Daniel,
On 4/27/22 16:21, Daniel Vetter wrote:
> On Thu, Apr 14, 2022 at 10:37:55PM +0200, Helge Deller wrote:
>> Hello dri-devel & dim users,
>
> Apologies for late reply, I'm way behind on stuff.
>
>> I committed this patch to the drm-misc-next branch:
>>
>> commit d6cd978f7e6b6f6895f8d0c4ce6
Hey! I will try to test this out ASAP on all of the HDR backlight machines I
have (so, many :) at some point this week, will let you know when
On Tue, 2022-04-26 at 15:30 +0300, Jouni Högander wrote:
> This patch set splits out static hdr metadata backlight range parsing
> from gpu/drm/amd/display
john.c.harri...@intel.com kirjoitti 27.4.2022 klo 19.55:
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new version. When merging, the revert would simply b
On Wed, Apr 27, 2022 at 9:07 AM Rob Clark wrote:
>
> On Tue, Apr 26, 2022 at 11:20 PM Christian König
> wrote:
> >
> > Am 26.04.22 um 20:50 schrieb Chia-I Wu:
> > > On Tue, Apr 26, 2022 at 11:02 AM Christian König
> > > wrote:
> > >> Am 26.04.22 um 19:40 schrieb Chia-I Wu:
> > >>> [SNIP]
> > >>>
On 27/04/2022 09:36, Tvrtko Ursulin wrote:
On 20/04/2022 18:13, Matthew Auld wrote:
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing
NEEDS_C
Hello Daniel,
On 4/27/22 17:29, Daniel Vetter wrote:
> On Wed, Apr 20, 2022 at 09:24:11AM +0200, Javier Martinez Canillas wrote:
>> Learning about the DRM subsystem could be quite overwhelming for newcomers
>> but there are lots of useful talks, slides and articles available that can
>> help to un
On 25/04/2022 17:24, Ramalingam C wrote:
Capture the impact of memory region preference list of an object, on
their memory residency and Flat-CCS capability of the objects.
v2:
Fix the Flat-CCS capability of an obj with {lmem, smem} preference
list [Thomas]
Signed-off-by: Ramalingam C
cc
From: John Harrison
First release of GuC for DG2.
Signed-off-by: John Harrison
CC: Tomasz Mistat
CC: Ramalingam C
CC: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/g
From: John Harrison
This reverts commit 55c7f980e48e56861496526e02ed5bbfdac49ede.
The CI topic branch within drm-top contains an old patch for
supporting GuC on DG2. That needs to be dropped and an updated patch
merged to drm-gt-next. Hence this patch reverts it so the new patch
can be sent in i
From: John Harrison
Add GuC firmware for DG2.
Note that an older version of this patch exists in the CI topic
branch. Hence this set includes a revert of that patch before applying
the new version. When merging, the revert would simply be dropped and
the corresponding patch in the topic branch w
Am Mittwoch, dem 27.04.2022 um 15:09 +0100 schrieb Daniel Thompson:
> Since it's inception in 2012 it has been understood that the DRM GEM CMA
> helpers do not depend on CMA as the backend allocator. In fact the first
> bug fix to ensure the cma-helpers work correctly with an IOMMU backend
> appear
On 25/04/2022 17:24, Ramalingam C wrote:
Capture the eviction details for Flat-CCS capable, lmem objects.
v2:
Fix the Flat-ccs capbility of lmem obj with smem residency
possibility [Thomas]
Signed-off-by: Ramalingam C
cc: Thomas Hellstrom
cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/
On Tue, Apr 26, 2022 at 11:20 PM Christian König
wrote:
>
> Am 26.04.22 um 20:50 schrieb Chia-I Wu:
> > On Tue, Apr 26, 2022 at 11:02 AM Christian König
> > wrote:
> >> Am 26.04.22 um 19:40 schrieb Chia-I Wu:
> >>> [SNIP]
> >> Well I just send a patch to completely remove the trace point.
> >
On Thu, Apr 21, 2022 at 09:10:02PM +0200, Christian König wrote:
> drm_gem_plane_helper_prepare_fb() was using
> drm_atomic_set_fence_for_plane() which ignores all implicit fences when an
> explicit fence is already set. That's rather unfortunate when the fb still
> has a kernel fence we need to wa
On Wed, Apr 20, 2022 at 03:45:25PM -0700, Niranjana Vishwanathapura wrote:
On Thu, Mar 31, 2022 at 10:28:48AM +0200, Daniel Vetter wrote:
Adding a pile of people who've expressed interest in vm_bind for their
drivers.
Also note to the intel folks: This is largely written with me having my
subsy
On 27/04/2022 18:18, Matthew Auld wrote:
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given
kernel?
I assume older kernels are going to reject object creation if we use
this flag?
On 27/04/2022 07:48, Lionel Landwerlin wrote:
One question though, how do we detect that this flag
(I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) is accepted on a given kernel?
I assume older kernels are going to reject object creation if we use
this flag?
From some offline discussion with Lionel
On 2022-04-27 06:52, Pekka Paalanen wrote:
> Hi Ville and Alex,
>
> thanks for the replies. More below.
>
> TL;DR:
>
> My take-away from this is that I should slam 'max bpc' to the max by
> default, and offer a knob for the user in case they want to lower it.
>
>
> On Tue, 26 Apr 2022 20:55
On Wed, Apr 27, 2022 at 08:55:07AM +0200, Christian König wrote:
> Well usually we increment the drm minor version when adding some new flags
> on amdgpu.
>
> Additional to that just one comment from our experience with that: You don't
> just need one flag, but two. The first one is a hint which s
On Wed, Apr 20, 2022 at 09:24:11AM +0200, Javier Martinez Canillas wrote:
> Learning about the DRM subsystem could be quite overwhelming for newcomers
> but there are lots of useful talks, slides and articles available that can
> help to understand the needed concepts and ease the learning curve.
>
On 2022-04-27 04:08, Ryan Lin wrote:
Disable ABM feature when the system is running on AC mode to get the more
perfect contrast of the display.
v2: remove "UPSTREAM" from the subject.
v3: adv->pm.ac_power updating by amd gpu_acpi_event_handler.
V4: Add the file I lost to fix the build error
Am 27.04.22 um 17:02 schrieb Matthew Auld:
On 27/04/2022 07:55, Christian König wrote:
Well usually we increment the drm minor version when adding some new
flags on amdgpu.
Additional to that just one comment from our experience with that:
You don't just need one flag, but two. The first one
On Tue, Apr 19, 2022 at 11:40:41PM +0300, Dmitry Osipenko wrote:
> On 4/19/22 10:22, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Introduce a common DRM SHMEM shrinker. It allows to reduce code
> >> duplication among DRM drivers that implement theirs o
On 27/04/2022 07:55, Christian König wrote:
Well usually we increment the drm minor version when adding some new
flags on amdgpu.
Additional to that just one comment from our experience with that: You
don't just need one flag, but two. The first one is a hint which says
"CPU access needed" an
On Mon, Apr 18, 2022 at 10:18:54PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> On 4/18/22 21:38, Thomas Zimmermann wrote:
> > Hi
> >
> > Am 18.04.22 um 00:37 schrieb Dmitry Osipenko:
> >> Replace drm_gem_shmem locks with the reservation lock to make GEM
> >> lockings more consistent.
> >>
> >> Pre
Applied. Thanks!
Alex
On Wed, Apr 27, 2022 at 3:12 AM Marek Marczykowski-Górecki
wrote:
>
> While technically Xen dom0 is a virtual machine too, it does have
> access to most of the hardware so it doesn't need to be considered a
> "passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BAR
On 2022-04-26 22:31, Hangyu Hua wrote:
On 2022/4/26 22:55, Andrey Grodzovsky wrote:
On 2022-04-25 22:54, Hangyu Hua wrote:
On 2022/4/25 23:42, Andrey Grodzovsky wrote:
On 2022-04-25 04:36, Hangyu Hua wrote:
When drm_sched_job_add_dependency() fails, dma_fence_put() will be
called
internall
Hi Dmitry
Thanks for fixing it up.
I agree about the indentation issue.
And yes even wb_idx missing in TP_ARGS seems like a geniune miss.
But the weird part is it did not break my compilation. I tested even now
without your fix.
Am I missing something to be enabled in my config to replicate
On Tue, Apr 26, 2022 at 01:40:31PM +0530, Jagan Teki wrote:
> On Tue, Apr 26, 2022 at 1:24 PM Paul Kocialkowski
> wrote:
> >
> > Hi,
> >
> > On Thu 21 Apr 22, 10:59, Paul Kocialkowski wrote:
> > > Hi Maxime,
> > >
> > > On Thu 21 Apr 22, 10:23, Maxime Ripard wrote:
> > > > On Thu, Apr 21, 2022 at
LGTM
Acked-by: Siva Mullati
On 06/04/22 14:48, Vivekanandan, Balasubramani wrote:
> When copying RSA use io memcpy functions if the destination address
> contains a GPU local memory address. Considering even the source
> address can be on local memory, a bounce buffer is used to copy from io
> t
On Wed, Apr 27, 2022 at 05:23:22PM +0300, Jani Nikula wrote:
> On Wed, 27 Apr 2022, Daniel Vetter wrote:
> > On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> >> On Mon, 11 Apr 2022, Alex Deucher wrote:
> >> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede
> >> > wrote:
> >> >>
> >>
On Wed, 27 Apr 2022, Daniel Vetter wrote:
> On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
>> On Mon, 11 Apr 2022, Alex Deucher wrote:
>> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
>> >>
>> >> Hi,
>> >>
>> >> On 4/8/22 17:11, Alex Deucher wrote:
>> >> > On Fri, Apr 8, 2
On Thu, Apr 14, 2022 at 10:37:55PM +0200, Helge Deller wrote:
> Hello dri-devel & dim users,
Apologies for late reply, I'm way behind on stuff.
> I committed this patch to the drm-misc-next branch:
>
> commit d6cd978f7e6b6f6895f8d0c4ce6e5d2c8e979afe
> video: fbdev: fbmem: fix pointer referen
Replace the inner loop of drm_fb_swab() with helper functions that
swap the bytes in each pixel. This will allow to share the outer
loop with other conversion helpers.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 60 +
1 file changed, 35
Provide format-independent conversion helpers for system and I/O
memory. Implement most existing helpers on top of it. The source and
destination formats of each conversion is handled by a per-line
helper that is given to the generic implementation.
Signed-off-by: Thomas Zimmermann
---
drivers/g
Give each per-line conversion helper pointers of type void and the
number of pixels in the line. Remove the unused swab parameters.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 87 +
1 file changed, 50 insertions(+), 37 deletions(-)
diff
Move all format-specific handling in per-line conversion functions and
share the overall loop among conversion helpers. This is another step
towards composable format conversion.
Thomas Zimmermann (4):
drm/format-helper: Implement drm_fb_swab() with per-line helpers
drm/format-helper: Remove
Implement per-pixel byte swapping in a separate conversion helper
for the single function that requires it. Select the correct helper
for each conversion.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 32 +
1 file changed, 24 insertions(+)
On Wed, Apr 13, 2022 at 06:12:59PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer
>
> Instead of relying on it getting pulled in indirectly.
>
> Signed-off-by: Michel Dänzer
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/tiny/bochs.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Since it's inception in 2012 it has been understood that the DRM GEM CMA
helpers do not depend on CMA as the backend allocator. In fact the first
bug fix to ensure the cma-helpers work correctly with an IOMMU backend
appeared in 2014. However currently the documentation for
drm_gem_cma_create() tal
On Thu, Apr 14, 2022 at 01:24:30PM +0300, Jani Nikula wrote:
> On Mon, 11 Apr 2022, Alex Deucher wrote:
> > On Mon, Apr 11, 2022 at 6:18 AM Hans de Goede wrote:
> >>
> >> Hi,
> >>
> >> On 4/8/22 17:11, Alex Deucher wrote:
> >> > On Fri, Apr 8, 2022 at 10:56 AM Hans de Goede
> >> > wrote:
> >> >
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