On Thu, Jun 18, 2020 at 1:57 AM Andrey Lebedev wrote:
>
> From: Andrey Lebedev
>
> Some pp or gp jobs can be successfully repeated even after they time outs.
> Introduce lima module parameter to specify number of times a job can hang
> before being dropped.
>
> Signed-off-by: Andrey Lebedev
> --
On Wed, Jun 17, 2020 at 1:53 PM Eric Anholt wrote:
>
> Previously the address space went from 16M to ~0u, but with the
> refactor one of the 'f's was dropped, limiting us to 256MB.
> Additionally, the new interface takes a start and size, not start and
> end, so we can't just copy and paste.
>
> F
On 6/17/20 8:29 PM, Thomas Zimmermann wrote:
Hi
Am 17.06.20 um 11:22 schrieb Rong Chen:
On Wed, Jun 17, 2020 at 08:28:02AM +0200, Thomas Zimmermann wrote:
Hi Emil
Am 16.06.20 um 17:14 schrieb Emil Velikov:
Hi Thomas,
On Tue, 16 Jun 2020 at 15:26, Thomas Zimmermann wrote:
The original m
From: Roy Spliet
[ Upstream commit e4337877c5d578722c0716f131fb774522013cf5 ]
When allocation for mdp5_kms fails, calling mdp5_destroy() leads to undefined
behaviour, likely a nullptr exception or use-after-free troubles.
Signed-off-by: Roy Spliet
Reviewed-by: Abhinav Kumar
Signed-off-by: Rob
From: Jernej Skrabec
[ Upstream commit 54e1e06bcf1cf6e7ac3f86daa5f7454add24b494 ]
m divider in DDC clock register is 4 bits wide. Fix that.
Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Link:
https://
From: Jon Hunter
[ Upstream commit d8207c155a7c6015eb7f43739baa7dfb1fa638af ]
If probing the LP885x backlight fails after the regulators have been
enabled, then the following warning is seen when releasing the
regulators ...
WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051
_regulator
From: Roy Spliet
[ Upstream commit e4337877c5d578722c0716f131fb774522013cf5 ]
When allocation for mdp5_kms fails, calling mdp5_destroy() leads to undefined
behaviour, likely a nullptr exception or use-after-free troubles.
Signed-off-by: Roy Spliet
Reviewed-by: Abhinav Kumar
Signed-off-by: Rob
From: Jon Hunter
[ Upstream commit d8207c155a7c6015eb7f43739baa7dfb1fa638af ]
If probing the LP885x backlight fails after the regulators have been
enabled, then the following warning is seen when releasing the
regulators ...
WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051
_regulator
From: Jernej Skrabec
[ Upstream commit 54e1e06bcf1cf6e7ac3f86daa5f7454add24b494 ]
m divider in DDC clock register is 4 bits wide. Fix that.
Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Link:
https://
From: Roy Spliet
[ Upstream commit e4337877c5d578722c0716f131fb774522013cf5 ]
When allocation for mdp5_kms fails, calling mdp5_destroy() leads to undefined
behaviour, likely a nullptr exception or use-after-free troubles.
Signed-off-by: Roy Spliet
Reviewed-by: Abhinav Kumar
Signed-off-by: Rob
From: Jon Hunter
[ Upstream commit d8207c155a7c6015eb7f43739baa7dfb1fa638af ]
If probing the LP885x backlight fails after the regulators have been
enabled, then the following warning is seen when releasing the
regulators ...
WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051
_regulator
From: Jernej Skrabec
[ Upstream commit 54e1e06bcf1cf6e7ac3f86daa5f7454add24b494 ]
m divider in DDC clock register is 4 bits wide. Fix that.
Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Link:
https://
From: Ben Skeggs
[ Upstream commit a1ef8bad506e4ffa0c57ac5f8cb99ab5cbc3b1fc ]
This is a SOR register, and not indexed by the bound head.
Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.
Signed-off-by: Ben Skeggs
Signed-off-by: Sasha Levin
---
dri
From: Nicholas Kazlauskas
[ Upstream commit a24eaa5c51255b344d5a321f1eeb3205f2775498 ]
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML
From: Roy Spliet
[ Upstream commit e4337877c5d578722c0716f131fb774522013cf5 ]
When allocation for mdp5_kms fails, calling mdp5_destroy() leads to undefined
behaviour, likely a nullptr exception or use-after-free troubles.
Signed-off-by: Roy Spliet
Reviewed-by: Abhinav Kumar
Signed-off-by: Rob
From: Jon Hunter
[ Upstream commit d8207c155a7c6015eb7f43739baa7dfb1fa638af ]
If probing the LP885x backlight fails after the regulators have been
enabled, then the following warning is seen when releasing the
regulators ...
WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051
_regulator
From: Jernej Skrabec
[ Upstream commit 54e1e06bcf1cf6e7ac3f86daa5f7454add24b494 ]
m divider in DDC clock register is 4 bits wide. Fix that.
Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
Link:
https://
From: Colin Ian King
[ Upstream commit 291ddeb621e4a9f1ced8302a777fbd7fbda058c6 ]
Currently the switch statement for format->cpp[0] value 4 assigns
color_index which is never read again and then falls through to the
default case and returns. This looks like a missing break statement
bug. Fix thi
From: Nicholas Kazlauskas
[ Upstream commit a24eaa5c51255b344d5a321f1eeb3205f2775498 ]
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML
From: Ben Skeggs
[ Upstream commit a1ef8bad506e4ffa0c57ac5f8cb99ab5cbc3b1fc ]
This is a SOR register, and not indexed by the bound head.
Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.
Signed-off-by: Ben Skeggs
Signed-off-by: Sasha Levin
---
dri
From: Roy Spliet
[ Upstream commit e4337877c5d578722c0716f131fb774522013cf5 ]
When allocation for mdp5_kms fails, calling mdp5_destroy() leads to undefined
behaviour, likely a nullptr exception or use-after-free troubles.
Signed-off-by: Roy Spliet
Reviewed-by: Abhinav Kumar
Signed-off-by: Rob
From: Bjorn Andersson
[ Upstream commit 20aebe83698feb107d5a66b6cfd1d54459ccdfcf ]
rd_full should be defined outside the CONFIG_DEBUG_FS region, in order
to be able to link the msm driver even when CONFIG_DEBUG_FS is disabled.
Fixes: e515af8d4a6f ("drm/msm: devcoredump should dump MSM_SUBMIT_BO
From: Thierry Reding
[ Upstream commit 21454fe697fde188ad6fb541f94b9838fa73ab38 ]
Tegra firmware doesn't actually use any version numbers and passing -1
causes the existing firmware binaries not to be found. Use version 0 to
find the correct files.
Fixes: ef16dc278ec2 ("drm/nouveau/gr/gf100-: s
From: Jon Hunter
[ Upstream commit d8207c155a7c6015eb7f43739baa7dfb1fa638af ]
If probing the LP885x backlight fails after the regulators have been
enabled, then the following warning is seen when releasing the
regulators ...
WARNING: CPU: 1 PID: 289 at drivers/regulator/core.c:2051
_regulator
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next
head: f59073f6df9b07d94917221486cf5929efa6b315
commit: a5cc9a9321cb7c32ed9d8f6f82e82376bcc04f81 [319/414] drm/amd/powerplay:
update powerplay table for sienna_cichlid
config: i386-randconfig-s001-20200617 (attached as .config
https://bugzilla.kernel.org/show_bug.cgi?id=208205
--- Comment #4 from Automne von Einzbern (mar...@automne.me) ---
Also on Kernel 5.8-rc1
--
You are receiving this mail because:
You are watching the assignee of the bug.
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Hi Rob,
On Wed, Jun 17, 2020 at 04:34:55PM -0600, Rob Herring wrote:
> On Thu, Jun 11, 2020 at 12:23:56PM +0200, Ricardo Cañuelo wrote:
> > Make the ports node optional, since there are some DTs that don't define
> > any ports for ti,tfp410.
>
> Only arch/arm/boot/dts/dove-sbc-a510.dts AFAICT...
On Fri, 12 Jun 2020 09:22:17 +0200, Matthias Schiffer wrote:
> Add the Tianma Micro-electronics TM070JVHG33 7.0" WXGA display to the
> panel-simple compatible list.
>
> Signed-off-by: Matthias Schiffer
> ---
>
> v2: no changes
>
> .../devicetree/bindings/display/panel/panel-simple.yaml
On Fri, 12 Jun 2020 09:22:16 +0200, Matthias Schiffer wrote:
> Add the CDTech Electronics displays S070PWS19HP-FC21 (7.0" WSVGA) and
> S070SWV29HG-DC44 (7.0" WVGA) to the panel-simple compatible list.
>
> Signed-off-by: Matthias Schiffer
> ---
>
> v2: no changes
>
> .../devicetree/bindings/dis
Use a bit-mask of EOF irqs to determine when all required idmac
channel EOFs have been received for a tile conversion, and only do
tile completion processing after all EOFs have been received. Otherwise
it was found that a conversion would stall after the completion of a
tile and the start of the n
RGB32 and BGR32 formats were inadvertently removed from the switch
statement in ipu_pixelformat_to_colorspace(). Restore them.
Fixes: a59957172b0c ("gpu: ipu-v3: enable remaining 32-bit RGB V4L2 pixel
formats")
Signed-off-by: Steve Longerbeam
---
drivers/gpu/ipu-v3/ipu-common.c | 2 ++
1 file c
Combine the rotate_irq() and norotate_irq() handlers into a single
eof_irq() handler.
Signed-off-by: Steve Longerbeam
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 58 +-
1 file changed, 20 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c
On Mon, Jun 15, 2020 at 11:38:07AM +0200, Ricardo Cañuelo wrote:
> Hi Laurent,
>
> Thanks for reviewing the patch
>
> On Thu, 2020-06-11 at 19:08 +0300, Laurent Pinchart wrote:
> > Hi Ricardo,
> >
> > Thank you for the patch.
> >
> > On Thu, Jun 11, 2020 at 12:23:56PM +0200, Ricardo Cañuelo wro
On Thu, Jun 11, 2020 at 12:23:56PM +0200, Ricardo Cañuelo wrote:
> Make the ports node optional, since there are some DTs that don't define
> any ports for ti,tfp410.
Only arch/arm/boot/dts/dove-sbc-a510.dts AFAICT... It should be updated
IMO.
>
> Signed-off-by: Ricardo Cañuelo
> ---
> Docume
Hi Dave, Daniel,
Fixes for 5.8.
The following changes since commit 8d286e2ff4400d313955b4203fc640ca6fd9228b:
Merge tag 'drm-intel-next-fixes-2020-06-04' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2020-06-08 11:59:57
+1000)
are available in the Git repository at:
git://
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes.
This code was detected with the help of Coccinelle and, audited and
fixed manually.
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/i915/i915_query.c | 3 +--
1 file chang
Hi Philpp,
Please disregard this patch. A better solution to a busy wait with a
spin lock held is to wait for all required EOF interrupts before doing
tile completion processing. I will submit a new patch series.
Steve
On 6/9/20 5:51 PM, Steve Longerbeam wrote:
Call ipu_idmac_wait_busy() o
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes.
This code was detected with the help of Coccinelle and, audited and
fixed manually.
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/virtio/virtgpu_gem.c | 3 +--
1 file ch
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes.
This code was detected with the help of Coccinelle and, audited and
fixed manually.
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 2 +-
1 file
On Tue, Jun 09, 2020 at 04:13:49PM +0300, Dmitry Osipenko wrote:
> Most of Host1x devices have at least one memory client. These clients
> are directly connected to the memory controller. The new interconnect
> properties represent the memory client's connection to the memory
> controller.
>
> Sig
Previously the address space went from 16M to ~0u, but with the
refactor one of the 'f's was dropped, limiting us to 256MB.
Additionally, the new interface takes a start and size, not start and
end, so we can't just copy and paste.
Fixes regressions in dEQP-VK.memory.allocation.random.*
Fixes: cc
We don't want it under CONFIG_DRM_MSM_GPU_STATE, we need it all the
time (like the other GPUs do).
Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization")
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
On Wed, Jun 17, 2020 at 1:16 PM Eric Anholt wrote:
>
> On Thu, Apr 9, 2020 at 4:34 PM Jordan Crouse wrote:
> >
> > Refactor how address space initialization works. Instead of having the
> > address space function create the MMU object (and thus require separate but
> > equal functions for gpummu
On Wed, May 27, 2020 at 9:49 AM Maxime Ripard wrote:
>
> The BCM283x SoCs have a display pipeline composed of several controllers
> with device tree bindings that are supported by Linux.
>
> Now that we have the DT validation in place, let's split into separate
> files and convert the device tree
On Thu, Apr 9, 2020 at 4:34 PM Jordan Crouse wrote:
>
> Refactor how address space initialization works. Instead of having the
> address space function create the MMU object (and thus require separate but
> equal functions for gpummu and iommu) use a single function and pass the
> MMU struct in. M
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next
head: f59073f6df9b07d94917221486cf5929efa6b315
commit: 00e86cf4bb21d5904053da0c2327dbcfa21f22ca [317/414] drm/amd/powerplay:
move powerplay table operation out of smu_v11_0.c
config: i386-randconfig-s001-20200617 (attached as
On Wed, Jun 17, 2020 at 8:36 AM Steven Price wrote:
>
> On 17/06/2020 15:15, Krzysztof Kozlowski wrote:
> > On Wed, May 27, 2020 at 04:43:34PM -0400, Alyssa Rosenzweig wrote:
> >> Reviewed-by: Alyssa Rosenzweig
> >>
> >> On Wed, May 27, 2020 at 10:05:44PM +0200, Krzysztof Kozlowski wrote:
> >>> T
On Wed, 17 Jun 2020 at 07:28, Thomas Zimmermann wrote:
> Maybe I can write a better commit message to highlight the change.
>
That would be amazing, thank you.
Emil
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Hi Stephen,
On Wed, 17 Jun 2020 at 08:03, Stephen Rothwell wrote:
>
> Hi Thomas,
>
> On Wed, 17 Jun 2020 08:33:24 +0200 Thomas Zimmermann
> wrote:
> >
> > We recently dropped the _unlock() suffix from drm_gem_object_put(). This
> > patch should be ok.
>
> Yes, but what it shows is that the drm-
Applied. Thanks!
Alex
On Wed, Jun 17, 2020 at 9:10 AM Chen Tao wrote:
>
> Fix memory leak in amdgpu_debugfs_gpr_read not freeing data when
> amdgpu_virt_enable_access_debugfs failed.
>
> Fixes: 95a2f917387a2 ("drm/amdgpu: restrict debugfs register accessunder
> SR-IOV")
> Signed-off-by: Chen T
On Thu, Jun 18, 2020 at 12:58:33AM +0800, Cyrus Lien wrote:
> On Tue, Jun 9, 2020 at 10:58 PM Ville Syrjälä
> wrote:
>
> > On Tue, Jun 09, 2020 at 03:57:04AM +0800, Cyrus Lien wrote:
> > > According to EDID spec, table 3.26, byte #6 and #8, which said "Minimum
> > > rate value shall be less than
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes.
This code was detected with the help of Coccinelle and, audited and
fixed manually.
Signed-off-by: Gustavo A. R. Silva
---
include/linux/fb.h | 5 +++--
1 file changed, 3 inserti
>-Original Message-
>From: charante=codeaurora@mg.codeaurora.org
> On Behalf Of Charan Teja
>Kalla
>Sent: Wednesday, June 17, 2020 2:29 AM
>To: Ruhl, Michael J ; Sumit Semwal
>; open list:DMA BUFFER SHARING FRAMEWORK
>; DRI mailing list de...@lists.freedesktop.org>
>Cc: Linaro MM SIG ;
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next
head: f59073f6df9b07d94917221486cf5929efa6b315
commit: 5872ef0b03247fe659226973998ff28e835afbe4 [333/414] drm/amd/powerplay:
forbid to use pr_err/warn/info/debug
config: arc-allyesconfig (attached as .config)
compiler: arc-elf-gcc (G
On Tue, Jun 9, 2020 at 10:58 PM Ville Syrjälä
wrote:
> On Tue, Jun 09, 2020 at 03:57:04AM +0800, Cyrus Lien wrote:
> > According to EDID spec, table 3.26, byte #6 and #8, which said "Minimum
> > rate value shall be less than or equal to maximum rate value". The
> minimum
> > horizontal/vertical r
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
master
head: 5fcb9628fd1227a5f11d87171cb1b8b5c414d9d9
commit: c422a628925d9733b0807d803133fb78a0a0f707 [953/2089] drm/amdgpu: rename
macro for VCN2.0 2.5 and 3.0
config: i386-randconfig-s001-20200617 (attached as
Fixes: c422a628925d ("drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0")
Signed-off-by: kernel test robot
---
vcn_v2_5.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 261afbb504bd0
From: Colin Ian King
Object drm_mode is allocated by the call to drm_mode_find_dmt
(via the call to drm_mode_duplicate and drm_mode_create). The
object is never free'd and hence causes a small memory leak.
Fix this by kfree'ing drm_mode once it is no longer required.
Addresses-Coverity: ("Resour
The debug0 and ipversion fields of the mxsfb_devdata structure are
unused. Remove them.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 4
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 --
2 files changed, 6 deletions(-)
The mxsfb_set_pixel_fmt() and mxsfb_set_bus_fmt() functions both deal
with format configuration, are always called in a row from
mxsfb_crtc_mode_set_nofb(), and set fields from the LCDC_CTRL register.
This requires a read-modify-update cycle in mxsfb_set_bus_fmt(). Make
this more efficient by mergi
The LCDIF present in the i.MX6SX has extra features compared to
the i.MX28. It has however lost its IP version register, so no official
version number is known. Bump the version to MXSFB_V6 following the i.MX
version, in preparation for support for the additional features.
Signed-off-by: Laurent P
This is a cosmetic change only, no code change is included.
Signed-off-by: Laurent Pinchart
Reviewed-by: Emil Velikov
Reviewed-by: Stefan Agner
---
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h
Extend the Kconfig option description by listing the i.MX7 and i.MX8M
SoCs, as they are supported by the same driver. Replace the list of SoCs
in the short description with just "(e)LCDIF LCD controller" to avoid
expanding it further in the future as support for more SoCs is added.
Signed-off-by:
The LCDIF in the i.MX6SX and i.MX7 have a second plane called the alpha
plane. Support it.
Signed-off-by: Laurent Pinchart
Reviewed-by: Emil Velikov
Reviewed-by: Stefan Agner
---
Changes since v1:
- Split whitespace cleanup to a separate patch
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 +
d
A fair number of includes are not needed. Drop them, and add a couple of
required includes that were included indirectly.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 +++-
drivers/gpu/drm/mxsfb/mxsfb_dr
The mxsfb driver is only used by OF platforms. Drop non-OF support.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/g
Enable vblank handling when the CRTC is turned on and disable it when it
is turned off. This requires moving vblank init after the KMS pipeline
initialisation, otherwise drm_vblank_init() gets called with 0 CRTCs.
Signed-off-by: Laurent Pinchart
Reviewed-by: Emil Velikov
Reviewed-by: Stefan Agne
The mxsfb_set_pixel_fmt() function returns an error when the selected
pixel format is unsupported. This can never happen, as such errors are
caught by the DRM core. Remove the error check.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/m
The vblank event is armed in the plane .atomic_update(). This works fine
as we have a single plane, and was the only option when the driver was
using the drm_simple_kms_helper helper, but will break as soon as
multiple planes are supported. Move it to CRTC .atomic_flush().
Signed-off-by: Laurent P
Replace the manual connector implementation based on drm_panel with the
drm_panel_bridge helper. This simplifies the mxsfb driver by removing
connector-related code, and standardizing all pipeline control
operations on bridges.
A hack is needed to get hold of the connector, as that's our only sour
The driver attempts agressive power management by enabling and disabling
the AXI clock around register accesses. This results in attempts to
enable and disable the clock in the IRQ handler, which is a no-go as
preparing or unpreparing the clock may sleep.
On the other hand, the driver enables the
The mxsfb_reset_block() function isn't special, pass it the
mxsfb_drm_private pointer instead of a pointer to the base address.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++--
1 file changed, 6 insert
The mxsfb_crtc.c file doesn't handle just the CRTC, but also the other
KMS objects. Rename it accordingly.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/Makefile | 2 +-
drivers/gpu/drm/mxsfb/{mxsfb_crtc.c =>
Replace the convoluted way to set the format and bus width through
difficult to read macros with more explicit ones. Also remove the
outdated comment related to the limitations on bus width setting as it
doesn't apply anymore (the bus width can be specified through the
display_info bus format).
Si
The DRM simple display pipeline helper only supports a single plane. In
order to prepare for support of the alpha plane on i.MX6SX and i.MX7,
move away from the helper. No new feature is added.
Signed-off-by: Laurent Pinchart
Reviewed-by: Emil Velikov
Reviewed-by: Stefan Agner
---
Changes since
Using BIT() is preferred over manual shifts as it's more readable,
handles the 1 << 31 case properly, and avoids other mistakes as shown by
the DEBUG0_HSYNC and DEBUG0_VSYNC bits (that are currently unused). Use
it.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Veli
Hello,
This patch series adds i.MX7 support to the mxsfb driver. The eLCDIF
instance found in the i.MX7 is backward-compatible with the already
supported LCDC v4, but has extended features amongst which the most
notable one is a second plane.
The first 10 patches (01/22 to 10/22) contain miscella
The LCDC_CTRL register is located at address 0x. Some of the
accesses to the register simply use the mxsfb->base address. Reference
the LCDC_CTRL register explicitly instead to clarify the code.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers
mxsfb_crtc.c defines several macros related to register addresses and
bit, which duplicates macros from mxsfb_regs.h. Use the macros from
mxsfb_regs.h instead and remove them.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_cr
Commit 8e93f1028d74 ("drm/mxsfb: Use drm_fbdev_generic_setup()")
replaced fbdev handling with drm_fbdev_generic_setup() but left
inclusion of the drm/drm_fb_cma_helper.h header. Remove it.
Fixes: 8e93f1028d74 ("drm/mxsfb: Use drm_fbdev_generic_setup()")
Signed-off-by: Laurent Pinchart
Reviewed-by
mxsfb_regs.h defines macros related to register bits. Some of them are
not used and don't clearly map to any particular register, so their
purpose isn't known. Remove them.
Signed-off-by: Laurent Pinchart
Reviewed-by: Stefan Agner
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/mxsfb/mxsfb_regs.
On Wed, Jun 17, 2020 at 05:20:14PM +0300, Dmitry Osipenko wrote:
> 17.06.2020 17:10, Thierry Reding пишет:
> > On Tue, Jun 16, 2020 at 09:39:19PM +0300, Dmitry Osipenko wrote:
> >> 16.06.2020 21:14, Thierry Reding пишет:
> >>> From: Thierry Reding
> >>>
> >>> As of commit 4dc55525b095 ("drm: plane
On 2020-05-30 05:10, Laurent Pinchart wrote:
> The LCDIF in the i.MX6SX and i.MX7 have a second plane called the alpha
> plane. Support it.
>
> Signed-off-by: Laurent Pinchart
Looks good to me.
Reviewed-by: Stefan Agner
--
Stefan
> ---
> Changes since v1:
>
> - Split whitespace cleanup to a
From: Colin Ian King
Function get_insert_time can return error values that are cast
to a u64. The checks of insert_time1 and insert_time2 check for
the errors but because they are u64 variables the check for less
than zero can never be true. Fix this by casting the value to s64
to allow of the ne
On Tue, Jun 16, 2020 at 5:15 AM Stephen Boyd wrote:
>
> Quoting Tanmay Shah (2020-06-11 18:50:26)
> > diff --git a/Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml
> > b/Documentation/devicetree/bindings/display/msm/dp-sc7180.yaml
> > new file mode 100644
> > index ..5fdb9
On Wed, Jun 17, 2020 at 11:58:10AM +0200, Daniel Vetter wrote:
> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
> > Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> > > Add enable/disable flip done functions and the flip done handler
> > > function which handles the flip do
Reviewed-by: Lyude Paul
Thanks for all the subtle fixes for broken MST displays, these are always my
favorite to find :)
On Wed, 2020-06-17 at 00:11 +0300, Imre Deak wrote:
> Atm, we clear the ACT sent flag in the sink's DPCD before updating the
> sink's payload table, along clearing the payload
On 2020-05-30 05:09, Laurent Pinchart wrote:
> Replace the manual connector implementation based on drm_panel with the
> drm_panel_bridge helper. This simplifies the mxsfb driver by removing
> connector-related code, and standardizing all pipeline control
> operations on bridges.
>
> A hack is nee
On 2020-06-17 5:58 a.m., Daniel Vetter wrote:
On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip
On 17/06/2020 15:15, Krzysztof Kozlowski wrote:
On Wed, May 27, 2020 at 04:43:34PM -0400, Alyssa Rosenzweig wrote:
Reviewed-by: Alyssa Rosenzweig
On Wed, May 27, 2020 at 10:05:44PM +0200, Krzysztof Kozlowski wrote:
There is no point to print deferred probe (and its failures to get
resources)
On Wed, May 27, 2020 at 04:43:34PM -0400, Alyssa Rosenzweig wrote:
> Reviewed-by: Alyssa Rosenzweig
>
> On Wed, May 27, 2020 at 10:05:44PM +0200, Krzysztof Kozlowski wrote:
> > There is no point to print deferred probe (and its failures to get
> > resources) as an error. Also there is no need to
On Tue, Jun 16, 2020 at 09:39:19PM +0300, Dmitry Osipenko wrote:
> 16.06.2020 21:14, Thierry Reding пишет:
> > From: Thierry Reding
> >
> > As of commit 4dc55525b095 ("drm: plane: Verify that no or all planes
> > have a zpos property") a warning is emitted if there's a mix of planes
> > with and
https://bugzilla.kernel.org/show_bug.cgi?id=206017
--- Comment #19 from udo (udo...@xs4all.nl) ---
Appears to work OK for me:
AMD Ryzen 5 3400G with Radeon Vega Graphics on Gigabyte X570 AORUS PRO,
Fedora 31, git mesa, kernel.org 5.6.x, etc
amdgpu.gttsize=8192 amdgpu.lockup_timeout=1000 amdgpu.g
Hi Jim,
Thanks for taking this on!
On 2020-06-16 21:55, Jim Quinlan wrote:
The new field in struct device 'dma_pfn_offset_map' is used to facilitate
the use of single or multiple pfn offsets between cpu addrs and dma addrs.
It subsumes the role of dev->dma_pfn_offset -- a uniform offset.
This
Hi
Am 17.06.20 um 11:22 schrieb Rong Chen:
> On Wed, Jun 17, 2020 at 08:28:02AM +0200, Thomas Zimmermann wrote:
>> Hi Emil
>>
>> Am 16.06.20 um 17:14 schrieb Emil Velikov:
>>> Hi Thomas,
>>>
>>> On Tue, 16 Jun 2020 at 15:26, Thomas Zimmermann wrote:
The original modesetting code set MIS
The new field in struct device 'dma_pfn_offset_map' is used to facilitate
the use of single or multiple pfn offsets between cpu addrs and dma addrs.
It subsumes the role of dev->dma_pfn_offset -- a uniform offset.
The function of_dma_get_range() has been modified to take two additional
arguments:
Patchset Summary:
Enhance a PCIe host controller driver. Because of its unusual design
we are foced to change dev->dma_pfn_offset into a more general role
allowing multiple offsets.
v5:
Commit "device core: Introduce multiple dma pfn offsets"
-- in of/address.c: "map_size = 0" => "*map_
On 16/06/2020 18:30, Tony Lindgren wrote:
* Tomi Valkeinen [200616 13:02]:
On 11/06/2020 17:00, Grygorii Strashko wrote:
I think, suspend might be fixed if all devices, which are now child of ti-sysc,
will do
pm_runtime_force_xxx() calls at noirq suspend stage by adding:
SET_NOIRQ_SY
Lontium LT9611 is a DSI to HDMI bridge which supports 2 DSI ports
and I2S port as input and one HDMI port as output
Reviewed-by: Rob Herring
Signed-off-by: Vinod Koul
---
.../display/bridge/lontium,lt9611.yaml| 176 ++
1 file changed, 176 insertions(+)
create mode 10064
Lontium Lt9611 is a DSI to HDMI bridge which supports two DSI ports and
I2S port as an input and HDMI port as output
Co-developed-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
Co-developed-by: Srinivas Kandagatla
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Vinod Koul
---
drivers/g
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