Also for reproducibility sake, can you give a pointer to the conv2d workload
you ran on the pynq? It might be worth looking into what's happening inside of
the Chisel-based VTA design so we can improve it. Adding @vegaluis to the
thread.
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@joyliu37 thanks for looking into this. There is at the moment two VTA design
sources: the initial design (which was used in the TVM and VTA papers) that was
generated with HLS - this is the design that one can test and deploy on the
Pynq/Ultra96 boards and run workloads like Resnet-18. We've
