I've already build websocket demo, and run our model with web assembly backend
in browser. but kernel is not tuned with this machine. I've read some tutorials
about android、cuda etc. I found rpc tracker is usefull.
Do we another way without rpc tracker that could be able to do tuning in
bro
Thanks @max1996 ! Somehow missed/overlooked this. Looks very promising.
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Hi @JosseVanDelm ,
Thanks for the post! Some thoughts:
>Right now a lot of calls to the HWlib are very inefficient, as they require a
>lot of data reformatting on the RISC-V before being accessible to the
>accelerator. It is weird/annoying that the data layout already gets specified
>from Re
Is it possible now to get the above "schedule" representation?
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hi @dream-math @jossevandelm @Julien
Thanks for some great collaboration, seems like there is significant community
interest in merging RISC-V support. Let's lay out some steps we can follow to
make this happen, and then we can discuss timelines.
1. To start with, I propose we explicitly tes
AutoTVM has an option to check the correctness in the past but has been removed
recently due to various of reasons. See the following PR for details
https://github.com/apache/tvm/pull/7250
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hi @Julien ,
With the help of @areusch , I have tried to make `tvm/tests/micro/qemu` work on
`qemu_riscv32`, and one month ago, it works for `test_compile_runtime` and
`test_relay` in `test_zephyr.py`, here is my
[code](https://github.com/Dream-math/Riscv-backend). But I find tvm code has
cha
@aca88
Looks like i'm running into the same issue :frowning:
Can you point to the code of VTA where they do this tensorization bypass?
Thanks!
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Hi @Amalik!
For Xilinx FPGA's you might also want to look into VITIS-AI Codegen.
https://tvm.apache.org/docs/deploy/vitis_ai.html
(I have no experience with this myself though)
best regards!
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