>= 9
+ {item.data, llvm::object::SectionedAddress::UndefSection});
+#else
+ item.data);
+#endif
if (res_or_err) {
auto info = res_or_err.get();
--
2.24.0
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e/Symbolize.h:58:63: note: no known
conversion for argument 2 from 'const uint64_t' {aka 'const long unsigned int'}
to 'llvm::object::SectionedAddress'
58 | object::SectionedAddress
ModuleOffset);
|
= ARMV7_MMU_DATA_READ_WRITE_CACHED \
}
+#define ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX 8
+
BSP_START_DATA_SECTION extern const arm_cp15_start_section_config
arm_cp15_start_mmu_config_table[];
--
2.24.1
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able.c
-
###
# Special Rules #
###
--
2.24.1
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to adapt the MMU
table.
I tested it on an old Pi1 and a Pi2 (loaded via a debugger - I still
have problems loading it via an image on the Pi2).
Best regards
Christian
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.
Best regards
Christian
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mcr &= ~SC16IS752_MCR_RTS;
}
}
if ((set & TIOCM_DTR) != 0) {
-mcr &= ~MCR_DTR;
+mcr &= ~SC16IS752_MCR_DTR;
}
if ((set & TIOCM_RTS) != 0) {
-mcr &= ~MCR_RTS;
+mcr &= ~SC16IS752_MCR_RTS;
}
if ((clear & TIOCM_DTR) != 0) {
-mcr |= MCR_DTR;
+mcr |= SC16IS752_MCR_DTR;
}
if ((clear & TIOCM_RTS) != 0) {
-mcr |= MCR_RTS;
+mcr |= SC16IS752_MCR_RTS;
}
write_reg(ctx, SC16IS752_MCR, &mcr, 1);
@@ -416,11 +419,11 @@ void sc16is752_interrupt_handler(void *arg)
read_2_reg(ctx, SC16IS752_IIR, SC16IS752_RXLVL, data);
iir = data[0];
- if ((iir & IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {
+ if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {
rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress);
}
- if ((iir & IIR_RX_INTERRUPT) != 0) {
+ if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) {
uint8_t buf[SC16IS752_FIFO_DEPTH];
uint8_t rxlvl = data[1];
--
2.18.0
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r */
+#define AM335X_I2C_IRQSTATUS_AL (1 << 0)
#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
-#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
-#define AM335X_I2C_IRQSTATUS_AL (1<<0)
#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
-#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
-#define AM335X_I2C_BUF_TXFIFO_CLR (0x0040u)
-#define AM335X_I2C_BUF_RXFIFO_CLR (0x4000u)
-#define AM335X_I2C_IRQSTATUS_AAS (1 << 9)
-#define AM335X_I2C_IRQSTATUS_BF (1 << 8)
+#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
#define AM335X_I2C_IRQSTATUS_STC (1 << 6)
-#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
-#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
-#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
+#define AM335X_I2C_IRQSTATUS_AERR (1 << 7)
+#define AM335X_I2C_IRQSTATUS_BF (1 << 8)
+#define AM335X_I2C_IRQSTATUS_AAS (1 << 9)
+#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
+#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
+#define AM335X_I2C_IRQSTATUS_BB (1 << 12)
+#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
+#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
#define AM335X_I2C_CON_STOP (0x0002u)
#define AM335X_I2C_CON_START (0x0001u)
#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
#define AM335X_I2C_CFG_MST_TX (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
-#define AM335X_I2C_IRQSTATUS_RAW_BB (0x1000u)
#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK
(0x0020u)
#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
--
2.21.0
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