Hello,
an user noticed that for example on the Xilinx Zynq 7000 BSP, the
rtems_cache_disable_data() doesn't work.
I had a look at this and managed to disable the L1 and L2 caches,
however, afterwards I got not that far. On the Cortex-A cores it seems
at least the L1 data cache is required to
> On Jun 14, 2024, at 5:47 AM, Sebastian Huber
> wrote:
>
> Hello,
>
> an user noticed that for example on the Xilinx Zynq 7000 BSP, the
> rtems_cache_disable_data() doesn't work.
>
> I had a look at this and managed to disable the L1 and L2 caches, however,
> afterwards I got not that far