Some of the architecture ports do not have implementations of
the context validation methods. The stubs do not reference the
parameter. This series of patches addresses that.
I separated them so each port is distinct.
--joel
Joel Sherrill (10):
bfin/include/rtems/score/cpuimpl.h: Address unuse
---
cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index f0e4088218..ba5d820016 100644
--- a/cpukit/score/cpu/i386/include/rtems/s
---
cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index 05628a2c0b..aaf34a3ce0 100644
--- a/cpukit/score/cpu/bfin/include/rtems/s
---
cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
index 8ded8c34e9..30c2c75f2b 100644
--- a/cpukit/score/cpu/moxie/include/rte
---
cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index 679ef452f4..870640864c 100644
--- a/cpukit/score/cpu/lm32/include/rtems/s
---
cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index ec90a41ae2..4bee157215 100644
--- a/cpukit/score/cpu/m68k/include/rtems/s
---
cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
index ad6b7ae615..d619eb6213 100644
--- a/cpukit/score/cpu/mips/include/rtems/s
---
cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
index 5ec528961c..3985c3cdb9 100644
--- a/cpukit/score/cpu/v850/include/rtems/s
---
cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
index 3e37c8f57d..ca87c61c2b 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpu
---
cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h | 4
1 file changed, 4 insertions(+)
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
index c49c637805..a29a519644 100644
--- a/cpukit/score/cpu/sparc64/inc
---
.../score/cpu/x86_64/include/rtems/score/cpuimpl.h | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
index e0e301b6bc..726a515d4e 100644
--- a/cpukit/
This commits add a new SiFive Unleashed bsp which follows the RV64IMAC RISC-V
Architecture. It can be run on QEMU provided by the RTEMS source builder's
devel/qemu bset. This BSP requires a minimum of 128MB (Default) of RAM size
which can be changed using the RISCV_RAM_REGION_SIZE configuration opt
This commit contains all the required information to build and run the
new BSP.
---
user/bsps/bsps-riscv.rst | 52
1 file changed, 52 insertions(+)
diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst
index 263796e..76b70ce 100644
--- a/user/bs
Moving it back to devel@.
It appears to be from this bit of magic in the same file which implements
it using a direct reference to register g7.
#elif defined(__sparc__)
#include
# define __get_tls() ({ void** __val; register uintptr_t g7 __asm__( "g7"
); __val = (void**) g7; __val; })
I honestl
flag it as a false positive.
g7 is a global register that is reserved for system / compiler use in
the sparc ABI
On Mon, Aug 21, 2023 at 2:17 PM Joel Sherrill wrote:
>
> Moving it back to devel@.
>
> It appears to be from this bit of magic in the same file which implements it
> using a direct r
On 22/8/2023 10:02 am, Gedare Bloom wrote:
> flag it as a false positive.
I agree.
> g7 is a global register that is reserved for system / compiler use in
> the sparc ABI
The reigster is set up by the operating system out of the view of Coverity. I
took the code from:
https://git.rtems.org/rtem
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