On 19/09/2022 18:39, OAR Tester wrote:
] test SHA512-224
] 4634270f707b6a54 daae7530460842e2 0e37ed265ceee9a4 2fa08086
] ../../../testsuites/libtests/sha/init.c: 356 memcmp(&r[0],
&test_sha512_224_results[i][0], sizeof(r)) == 0
This is an interesting failure. It could be a GCC or SIS bug.
-
Only clear the HSCTLR[TE] bit to take exceptions in A32 state. Keep the
other HSCTLR bits as is since they control the current execution.
Assume that the chip or boot loader did initialize this register
correctly.
Add comments.
---
bsps/arm/shared/start/start.S | 21 -
1 file
This procedure should be added to the Users Guide under the BSPs section.
Otherwise, it looks like I should coordinate with Padmarao to make sure
it's ok after I merged it
On Tue, Sep 20, 2022, 1:50 AM wrote:
> RTEMS SMP on the Microchip PolarFire Icicle Kit
>
> Test Procedure:
>
> 1. Create th
>
>
> Try the fileio, cdtest, nsecs, and paranoia samples next. If those
> look ok, it is highly likely that most of the single processor tests
> will run.
>
> fileio requires working console input.
>
I've tried them all, they look pretty fine. Fileio worked fine too.
Now work to get this all cle
I have pushed this patch set. Please check that the merge is OK and follow
up with an update to the Users Guide for those looking for this BSP.
Thanks.
On Tue, Sep 20, 2022 at 8:56 AM Joel Sherrill
wrote:
> This procedure should be added to the Users Guide under the BSPs section.
>
> Otherwise,
Hi Joel,
Sorry for the long delay.
I tried to reproduce the error locally. For me building rtems and rtems-libbsd
master for pc386 and pc686 works.
I get some undefined references for the 6-freebsd-12 branch though.
Which branch of rtems-libbsd did you use?
Best regards,
Jan
F
On Tue, Sep 20, 2022 at 12:43 PM wrote:
> Hi Joel,
>
>
>
> Sorry for the long delay.
>
> I tried to reproduce the error locally. For me building rtems and
> rtems-libbsd master for pc386 and pc686 works.
>
> I get some undefined references for the 6-freebsd-12 branch though.
>
> Which branch of r
On 20/9/2022 9:12 pm, Sebastian Huber wrote:
> Only clear the HSCTLR[TE] bit to take exceptions in A32 state. Keep the
> other HSCTLR bits as is since they control the current execution.
> Assume that the chip or boot loader did initialize this register
> correctly.
I think this change should hav
On 21/9/2022 3:03 am, Joel Sherrill wrote:
> I have pushed this patch set. Please check that the merge is OK and follow up
> with an update to the Users Guide for those looking for this BSP.
Thanks. Great to see the addition of this BSP.
I have updated the RSB to include this BSP. I have also add
Hi Joel,
> On Tue, 2022-09-20 at 12:03 -0500, Joel Sherrill wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> I have pushed this patch set. Please check that the merge is OK and
> follow up with an update to the Users Guide for those looking fo
Hi Chris,
Thank You for a tar file build, will try to build same using your repo.
Regards
Padmarao
> On Wed, 2022-09-21 at 14:34 +1000, Chris Johns wrote:
>
> On 21/9/2022 3:03 am, Joel Sherrill wrote:
> > I have pushed this patch set. Please check that the merge is OK and
> > follow up
> > wit
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