Remove the hard coded time limits in the SIS configurations which would
overrule the general tester settings (for example the--timeout command line
option).
---
tester/rtems/testing/bsps/erc32-sis.ini | 2 +-
tester/rtems/testing/bsps/gr740-sis.ini | 2 +-
tester/rtems/testing/bsps/grisc
On 4/7/2022 4:06 pm, Sebastian Huber wrote:
> On 04/07/2022 03:43, Chris Johns wrote:
>> On 1/7/2022 11:21 pm, Sebastian Huber wrote:
>>> Use the existing WRITE_SR() abstraction to access the interrupt group 0 and
>>> 1
>>> enable registers. This fixes the build for the AArch32 target.
>>> ---
>>
On 4/7/2022 4:08 pm, Sebastian Huber wrote:
> On 29/06/2022 15:07, Sebastian Huber wrote:
>> At some point during system initialization, the idle threads are created.
>> Afterwards, the boot processor basically executes within the context of an
>> idle
>> thread with thread dispatching disabled.
OK
Chris
On 4/7/2022 6:52 pm, Sebastian Huber wrote:
> Remove the hard coded time limits in the SIS configurations which would
> overrule the general tester settings (for example the--timeout command line
> option).
> ---
> tester/rtems/testing/bsps/erc32-sis.ini | 2 +-
> tester/rtems/test
The limit removed in sis and tsim is the simulated cpu time used. If not
using that, the behavior of the tester is to let the simulator run for so
much real processor time.
Replacing these with a command line argument is probably good but just
removing these mean these simulators will just run muc
On 5/7/2022 9:44 am, Joel Sherrill wrote:
> The limit removed in sis and tsim is the simulated cpu time used. If not using
> that, the behavior of the tester is to let the simulator run for so much real
> processor time.
>
> Replacing these with a command line argument is probably good but just
On 05/07/2022 00:33, Chris Johns wrote:
On 4/7/2022 4:08 pm, Sebastian Huber wrote:
On 29/06/2022 15:07, Sebastian Huber wrote:
At some point during system initialization, the idle threads are created.
Afterwards, the boot processor basically executes within the context of an idle
thread with
On 05/07/2022 03:08, Chris Johns wrote:
On 5/7/2022 9:44 am, Joel Sherrill wrote:
The limit removed in sis and tsim is the simulated cpu time used. If not using
that, the behavior of the tester is to let the simulator run for so much real
processor time.
Replacing these with a command line argu
On 5/7/2022 2:56 pm, Sebastian Huber wrote:
> On 05/07/2022 00:33, Chris Johns wrote:
>> On 4/7/2022 4:08 pm, Sebastian Huber wrote:
>>> On 29/06/2022 15:07, Sebastian Huber wrote:
At some point during system initialization, the idle threads are created.
Afterwards, the boot processor bas
On 5/7/2022 2:58 pm, Sebastian Huber wrote:
> On 05/07/2022 03:08, Chris Johns wrote:
>> On 5/7/2022 9:44 am, Joel Sherrill wrote:
>>> The limit removed in sis and tsim is the simulated cpu time used. If not
>>> using
>>> that, the behavior of the tester is to let the simulator run for so much
>>
On 05/07/2022 00:28, Chris Johns wrote:
On 4/7/2022 4:06 pm, Sebastian Huber wrote:
On 04/07/2022 03:43, Chris Johns wrote:
On 1/7/2022 11:21 pm, Sebastian Huber wrote:
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the
On 05/07/2022 07:14, Chris Johns wrote:
On 5/7/2022 2:58 pm, Sebastian Huber wrote:
On 05/07/2022 03:08, Chris Johns wrote:
On 5/7/2022 9:44 am, Joel Sherrill wrote:
The limit removed in sis and tsim is the simulated cpu time used. If not using
that, the behavior of the tester is to let the si
On 5/7/2022 4:02 pm, Sebastian Huber wrote:
> On 05/07/2022 07:14, Chris Johns wrote:
>> On 5/7/2022 2:58 pm, Sebastian Huber wrote:
>>> On 05/07/2022 03:08, Chris Johns wrote:
On 5/7/2022 9:44 am, Joel Sherrill wrote:
> The limit removed in sis and tsim is the simulated cpu time used. If
On 05/07/2022 08:23, Chris Johns wrote:
On 5/7/2022 4:02 pm, Sebastian Huber wrote:
On 05/07/2022 07:14, Chris Johns wrote:
On 5/7/2022 2:58 pm, Sebastian Huber wrote:
On 05/07/2022 03:08, Chris Johns wrote:
On 5/7/2022 9:44 am, Joel Sherrill wrote:
The limit removed in sis and tsim is the s
This particular state during a reconsider help request scheduler operation was
only covered by the existing test suites under some timing conditions.
---
testsuites/validation/tc-sched-smp.c | 137 ++-
1 file changed, 135 insertions(+), 2 deletions(-)
diff --git a/testsuit
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