Hello Duc,
just one remark.
On 6/27/22 05:34, Duc Doan wrote:
rtems_gpio_ctrl_t *ctrl0 = bsp_gpio_get_ctrl(60); //corresponds to
GPIOD pin 12 on F4
^ if your ctrl structure knows you are working with pin 60
rtems_gpio_write(ctrl, 60, RTEMS_GPIO_PIN_SET);
then you do not need to use it
Hello Christian and Karel,
On Mon, 2022-06-27 at 08:29 +0200, Christian MAUDERER wrote:
> Please think about whether you want to start at 0 or at 1!
>
I want it to start at 0.
>
> Be really careful with that syntax. If you use increasing numbers
> like
> you suggested, every controller would
Hello Duc,
Am 27.06.22 um 12:39 schrieb Duc Doan:
Hello Christian and Karel,
On Mon, 2022-06-27 at 08:29 +0200, Christian MAUDERER wrote:
Please think about whether you want to start at 0 or at 1!
I want it to start at 0.
Be really careful with that syntax. If you use increasing numbers
Hi
This patch set is generated by scripting which looks for files with the
RTEMS GPL, a single copyright line, and written by OAR, embedded brains,
Chris Johns, or Gedare Bloom. This is a good first step at relicensing
the easy to recognize files.
After doing this to all architectures, the next s
Updates #3053.
---
bsps/arm/shared/cache/cache-cp15.c| 25 ---
bsps/arm/shared/cache/cache-cp15.h| 25 ---
bsps/arm/shared/cache/cache-v7m.c | 25 ---
bsps/arm/shared/clock/clock-a9mpcore.c| 25
Updates #3053.
---
.../altera-cyclone-v/console/console-config.c | 25 ---
bsps/arm/altera-cyclone-v/i2c/i2cdrv-config.c | 25 ---
bsps/arm/altera-cyclone-v/i2c/i2cdrv-config.h | 25 ---
bsps/arm/altera-cyclone-v/i2c/i2cdrv.c| 25
Updates #3053.
---
bsps/arm/atsam/clock/systick-freq.c | 25 ---
bsps/arm/atsam/console/console.c | 25 ---
bsps/arm/atsam/console/debug-console.c| 25 ---
bsps/arm/atsam/i2c/atsam_i2c_bus.c| 25
Updates #3053.
---
bsps/arm/csb337/console/fbcons.c | 25 ++---
bsps/arm/csb337/include/sed1356.h| 25 ++---
bsps/arm/csb337/start/umonsupp.c | 25 ++---
bsps/arm/csb337/umon/tfsDriver.c | 25 ++---
Updates #3053.
---
bsps/arm/imx/console/console-config.c | 25 ---
bsps/arm/imx/i2c/imx-i2c.c| 25 ---
.../include/arm/freescale/imx/imx_ecspireg.h | 25 ---
.../include/arm/freescale/imx/imx_gpcreg.h| 25
Updates #3053.
---
bsps/arm/include/bsp/arm-a9mpcore-clock.h | 25 ---
bsps/arm/include/bsp/arm-a9mpcore-irq.h | 25 ---
bsps/arm/include/bsp/arm-a9mpcore-regs.h | 25 ---
bsps/arm/include/bsp/arm-a9mpcore-start.h | 25
Updates #3053.
---
bsps/arm/imxrt/start/bspstarthooks.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/bsps/arm/imxrt/start/bspstarthooks.c
b/bsps/arm/imxrt/start/bspstarthooks.c
index 244c13b063..684c263152 100644
--- a/bsps/arm/imxrt/start/bsp
Updates #3053.
---
bsps/arm/lpc176x/console/console-config.c | 25 ---
bsps/arm/lpc176x/include/bsp.h| 25 ---
bsps/arm/lpc176x/include/bsp/dma.h| 25 ---
bsps/arm/lpc176x/include/bsp/irq.h| 25
Updates #3053.
---
bsps/arm/raspberrypi/start/bspsmp.c | 25 +---
bsps/arm/raspberrypi/start/bspsmp_init.c | 25 +---
2 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/raspberrypi/start/bspsmp.c
b/bsps/arm/raspberrypi/start/b
Updates #3053.
---
bsps/arm/lpc24xx/console/console-config.c | 25 ---
bsps/arm/lpc24xx/console/uart-probe-1.c | 25 ---
bsps/arm/lpc24xx/console/uart-probe-2.c | 25 ---
bsps/arm/lpc24xx/console/uart-probe-3.c | 25
Updates #3053.
---
bsps/arm/lpc32xx/console/console-config.c | 25 ---
bsps/arm/lpc32xx/console/hsu.c| 25 ---
bsps/arm/lpc32xx/i2c/i2c.c| 25 ---
bsps/arm/lpc32xx/include/bsp.h| 25
Updates #3053.
---
.../realview-pbx-a9/console/console-config.c | 25 ---
.../realview-pbx-a9/console/console-polled.c | 25 ---
bsps/arm/realview-pbx-a9/include/bsp.h| 25 ---
.../arm/realview-pbx-a9/include/bsp/console.h | 25
Updates #3053.
---
bsps/arm/beagle/start/bspstart.c | 25 ++---
bsps/arm/beagle/start/bspstarthooks.c | 25 ++---
2 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/beagle/start/bspstart.c b/bsps/arm/beagle/start/bspstart.c
ind
On 6/26/2022 22:37, Chris Johns wrote:
On 24/6/2022 7:43 pm, Sebastian Huber wrote:
The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets. Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers. This fixe
On 6/27/2022 01:27, Sebastian Huber wrote:
On 27/06/2022 05:02, Chris Johns wrote:
On 24/6/2022 7:44 pm, Sebastian Huber wrote:
On 20.06.22 04:03, chr...@rtems.org wrote:
From: Chris Johns
---
bsps/include/dev/irq/arm-gicv3.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bsps
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