---
.../include/arm/freescale/imx/imx6ul_ccmreg.h | 152 ++
bsps/arm/imx/start/bspstart.c | 20 +++
spec/build/bsps/arm/imx/bspimx.yml| 1 +
3 files changed, 173 insertions(+)
create mode 100644 bsps/arm/imx/include/arm/freescale/imx/imx6ul_ccmreg.h
Some BSPs require that Clear_tm27_intr() is called in the interrupt
service routine.
Update #3269.
---
testsuites/validation/tx-call-within-isr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/testsuites/validation/tx-call-within-isr.c
b/testsuites/validation/tx-call-within-isr.c
index 22
---
bsps/arm/lpc32xx/include/bsp/boot.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/bsps/arm/lpc32xx/include/bsp/boot.h
b/bsps/arm/lpc32xx/include/bsp/boot.h
index bc8b13a5aa..3f1c3531b2 100644
--- a/bsps/arm/lpc32xx/include/bsp/boot.h
+++ b/bsps/arm/lpc32xx/include/bsp
The interrupt enables are used to implement a priority scheme in
bsp_interrupt_dispatch(). Enable interrupts through
bsp_interrupt_vector_enable() only if they are not already enabled to
not interfere with the priority scheme while
bsp_interrupt_vector_enable() is called during interrupt dispatchi
Provide custom bsp_interrupt_is_valid_vector() implementation since
several interrupt vectors are reserved.
---
bsps/arm/lpc32xx/include/bsp/irq.h | 4
bsps/arm/lpc32xx/irq/irq.c | 27 +++
2 files changed, 31 insertions(+)
diff --git a/bsps/arm/lpc32xx/includ
This helps to run the validation tests of the Interrupt Manager
directives.
---
bsps/arm/lpc32xx/include/tm27.h | 58 ++---
1 file changed, 39 insertions(+), 19 deletions(-)
diff --git a/bsps/arm/lpc32xx/include/tm27.h b/bsps/arm/lpc32xx/include/tm27.h
index 3ae09dec90
---
bsps/arm/lpc32xx/irq/irq.c | 48 +-
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index 2b047be559..959829b047 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@
Do not sporadically service interrupts configured as FIQ by the IRQ
interrupt dispatch.
---
bsps/arm/lpc32xx/irq/irq.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index e10393265b..947faca52c
On 06/06/2022 03:56, Chris Johns wrote:
+TFTP Files in the ``rtems-docs`` GIT
+
+
+``filesystem/trivial_ftp.rst``
+ The file contains the text of chapter*Trivial FTP Client Filesystem*
+ in the*RTEMS Filesystem Design Guide*.
+
+``images/filesystem/*``
+ The
On Sun, Jun 5, 2022 at 8:56 PM Chris Johns wrote:
> Hi Frank,
>
> Thanks for the documentation and the TFTP file system update.
>
> On 4/6/2022 1:22 am, Frank Kuehndel wrote:
> > From: Frank Kühndel
> >
> > ---
> > filesystem/index.rst | 1 +
> > filesystem/trivial_ftp.rst | 638 +++
Does the BSP doco in the User Manual need updating to mention the clock setting
and the required FDT?
This code fails silently and so documentation is fine or I think the user should
be alerted some other way.
Otherwise OK to push :)
Thanks
Chris
On 7/6/2022 11:05 pm, Christian Mauderer wrote:
OK
Thanks
Chris
On 8/6/2022 12:02 am, Sebastian Huber wrote:
> Do not sporadically service interrupts configured as FIQ by the IRQ
> interrupt dispatch.
> ---
> bsps/arm/lpc32xx/irq/irq.c | 23 +--
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/bsps/arm
From: Chris Johns
Updates #4661
---
spec/build/testsuites/libtests/exit03.yml | 20
spec/build/testsuites/libtests/grp.yml| 2 +
testsuites/libtests/exit03/exit03.doc | 11 ++
testsuites/libtests/exit03/exit03.scn | 5 +
testsuites/libtests/exit03/init.c | 122
libstdc++-v3/ChangeLog:
* crossconfig.m4 (*-rtems*): Enable TLS support for all RTEMS targets
except mips.
---
libstdc++-v3/crossconfig.m4 | 7 +++
1 file changed, 7 insertions(+)
diff --git a/libstdc++-v3/crossconfig.m4 b/libstdc++-v3/crossconfig.m4
index ae5283b7ad3..732f68
14 matches
Mail list logo