[PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration

Sponsored-By: Precidata --- tester/rtems/testing/bsps/stm32h7-stlink.ini | 43 1 file changed, 43 insertions(+) create mode 100644 tester/rtems/testing/bsps/stm32h7-stlink.ini diff --git a/tester/rtems/testing/bsps/stm32h7-stlink.ini b/tester/rtems/testing/bsps/stm32h7-st

[PATCH 1/2] tester/gdb: allow kill on the test end

Sponsored-By: Precidata --- tester/rt/config.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tester/rt/config.py b/tester/rt/config.py index a7b9ee3..8a433af 100644 --- a/tester/rt/config.py +++ b/tester/rt/config.py @@ -258,6 +258,7 @@ class file(config.file): script = self.expa

Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration

On 30/5/2022 7:35 am, Karel Gardas wrote: > Sponsored-By: Precidata > --- > tester/rtems/testing/bsps/stm32h7-stlink.ini | 43 > 1 file changed, 43 insertions(+) > create mode 100644 tester/rtems/testing/bsps/stm32h7-stlink.ini > > diff --git a/tester/rtems/testing/bsps/stm3

Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration

On 5/30/22 00:52, Chris Johns wrote: +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, target_posttest_command Should this be `requires =`? Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC I really tested it by modifying user ini file and it really

Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration

On 30/5/2022 9:07 am, Karel Gardas wrote: > On 5/30/22 00:52, Chris Johns wrote: >>> +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, >>> target_posttest_command >> >> Should this be `requires =`? > > Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC > I

Re: [PATCH 2/2] tester/bsps: add stm32h7-stlink family configuration

On 5/30/22 01:07, Karel Gardas wrote: On 5/30/22 00:52, Chris Johns wrote: +requires: bsp_tty_dev, bsp_gdb_script, target_pretest_command, target_posttest_command Should this be `requires =`? Indeed, very likely yes, but I'm wondering how it passed my testing. And IIRC I really tested it by

[PATCH 1/7] bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header File

--- bsps/arm/include/core_cm4.h | 1937 +++ 1 file changed, 1937 insertions(+) create mode 100644 bsps/arm/include/core_cm4.h diff --git a/bsps/arm/include/core_cm4.h b/bsps/arm/include/core_cm4.h new file mode 100644 index 00..dc840ebf22 --- /dev/null +++

[PATCH 3/7] bsps/stm32h7: move cache implementation from obj to BSPs own yml file

This is done in preparation for future Cortex-M4 based BSP variants which do not provide cache at all. Sponsored-By: Precidata --- spec/build/bsps/arm/stm32h7/bspnucleoh743zi.yml| 1 + spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 1 + spec/build/bsps/arm/stm32h7/bspstm32h757i-eval.y

[PATCH 2/7] bsps/stm32h7: enable cache and MPU only on Cortex-M7

Sponsored-By: Precidata --- bsps/arm/stm32h7/start/bspstarthooks.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c b/bsps/arm/stm32h7/start/bspstarthooks.c index ef26af5eba..dd8f544e52 100644 --- a/bsps/arm/stm32h7/start/bspstarthoo

[PATCH 4/7] bsps/stm32h7: include CMSIS Cortex-M4 header when required by configuration

Sponsored-By: Precidata --- bsps/arm/stm32h7/include/chip.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/bsps/arm/stm32h7/include/chip.h b/bsps/arm/stm32h7/include/chip.h index 26b067a3b7..ac579c0743 100644 --- a/bsps/arm/stm32h7/include/chip.h +++ b/bsps/arm/stm32h7/include/chip.h

[PATCH 5/7] bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSP

This is minimalist configuration for the stm32h757i-eval-m4 BSP provided here. The only general enhancement worth mention is a flash origin address configuration which is needed for simplification as M4 core boots from second flash bank which starts at 0x810 by default. The boot address of the

[PATCH 6/7] bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSP

This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata --- spec/build/bsps/arm/stm32h7/optenuart4.yml | 1 + spec/build/bsps/arm/stm32h7/optenuart5.yml | 1 + spec/build/bsps/arm/stm32h7/optenuart7.yml | 1 + spec/

[PATCH 7/7] bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSP

This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata --- spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml | 1 + spec/build/bsps/arm/stm32h7/optmemsdram2sz.yml | 1 + 2 files changed, 2 insertions(+) diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml b/spec/build/bsps/arm/stm

Re: [PATCH 2/7] bsps/arm: disable cache operations on Cortex-M4

On 5/23/22 14:45, Sebastian Huber wrote: On 16/05/2022 16:02, Karel Gardas wrote: ---   bsps/arm/shared/cache/cache-v7m.c | 22 ++   1 file changed, 22 insertions(+) diff --git a/bsps/arm/shared/cache/cache-v7m.c b/bsps/arm/shared/cache/cache-v7m.c index f5a9e208e5..100d387

AW: AW: [PATCH 1/1] kern_tc.c: th_generation starts with 1 after overflow for single-core

> On 27.05.22 11:49, gabriel.moy...@dlr.de wrote: > >> On 27.05.22 10:51, Sebastian Huber wrote: > >>> Hello Gabriel, > >>> > >>> the uniprocessor version uses an optimization at the reader side: > >>> > >>> #if defined(RTEMS_SMP) > >>> } while (gen == 0 || gen != th->th_generation); #else >

Re: AW: AW: [PATCH 1/1] kern_tc.c: th_generation starts with 1 after overflow for single-core

On 30/05/2022 08:29, gabriel.moy...@dlr.de wrote: On 27.05.22 11:49,gabriel.moy...@dlr.de wrote: On 27.05.22 10:51, Sebastian Huber wrote: Hello Gabriel, the uniprocessor version uses an optimization at the reader side: #if defined(RTEMS_SMP) } while (gen == 0 || gen != th->th_generat