Hello Vijay,
thanks for the update. I pushed it.
Best regards
Christian
On 24/09/2019 20:44, Vijay Kumar Banerjee wrote:
> ---
> user/bsps/arm/beagle.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/user/bsps/arm/beagle.rst b/user/bsps/arm/beagle.rst
> index
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel
---
Changes in v3:
- Remove bsps/riscv/frdme310arty/ directory and added support for
Freedom FE310 soc in common bsps/riscv/riscv/ directory
- Added #define RISCV_ENABLE_FRDME31