Hello,
The support for letting users input specific symbols
for coverage analysis is now working in my
cov-tester-support branch
https://github.com/thelunatic/rtems-tools/tree/cov-tester-support
Please have a look into the code and test it.
The user can input specific symbols with the --coverag
On Sun, 27 May 2018, 19:59 Vijay Kumar Banerjee,
wrote:
> Hello,
>
> The support for letting users input specific symbols
> for coverage analysis is now working in my
> cov-tester-support branch
>
> https://github.com/thelunatic/rtems-tools/tree/cov-tester-support
>
Brilliant Vijay, I'll take a
On Mon, 28 May 2018, 00:32 Cillian O'Donnell, wrote:
>
>
> On Sun, 27 May 2018, 19:59 Vijay Kumar Banerjee,
> wrote:
>
>> Hello,
>>
>> The support for letting users input specific symbols
>> for coverage analysis is now working in my
>> cov-tester-support branch
>>
>> https://github.com/thelunat
It sounds like great progress is being made but this thread is very long
and I am losing track of what needs committing.
Plus there is Chris' work to merge as well.
How close is everything to moving back to master on the main repo?
On Sun, May 27, 2018, 2:13 PM Vijay Kumar Banerjee
wrote:
>
>
On 28 May 2018 at 00:49, Joel Sherrill wrote:
> It sounds like great progress is being made but this thread is very long
> and I am losing track of what needs committing.
>
> We can start a new thread. :)
> Plus there is Chris' work to merge as well.
>
> How close is everything to moving back to
Hello Hesham,
this is probably a retired repository. For RTEMS testing please have a
look at the RTEMS tester:
https://docs.rtems.org/branches/master/user/tools/tester.html
https://git.rtems.org/rtems-tools/tree/tester
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178
Hello,
we currently have a riscv32-rtems* and riscv64-rtems* tool chain.
However, the RISC-V GCC is a bi-arch compiler, e.g. we have
riscv32-rtems5-gcc --print-multi-lib
.;
rv32i/ilp32;@march=rv32i@mabi=ilp32
rv32im/ilp32;@march=rv32im@mabi=ilp32
rv32iac/ilp32;@march=rv32iac@mabi=ilp32
rv32ima
Hello,
on which board do the RISC-V BSPs run? The memory is located at 0x1000_.
The FE310-G000 has the ROM at 0x2000_ and RAM (DTIM) at 0x8000_.
The FU540-C000 (and Qemu "virt") has the ROM at 0x2000_ and RAM
(DDR) at 0x8000_.
So, why is the memory at 0x1000_ and not
On 28/05/18 07:23, Sebastian Huber wrote:
I suggest to merge the two tool chains into one riscv-rtems* variant.
Unfortunately, this is not easy to do. The "config.sub" script doesn't
recognize a "riscv" machine.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchh
Hi,
(Re-ping regarding previous mail.)
Does anyone have an idea regarding if the psxtimer01 test can be
expected to report a time difference as described below, or if this is
something that is not expected and should be treated as a valid test
failure?
(Please also see related patch.)
--
Marti
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