From: Aaron Nyholm
---
rtemsbsd/sys/arm64/xilinx/versal_slcr.c | 30 +
rtemsbsd/sys/arm64/xilinx/versal_slcr.h | 6 +
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/rtemsbsd/sys/arm64/xilinx/versal_slcr.c
b/rtemsbsd/sys/arm64/xilinx/versal_slcr.c
in
Updated formatting.
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This looks good as far as the functional content is concerned. As a nit, it
looks like some unnecessary newlines were added in cgem_set_ref_clk() and
the added if() conditional braces are inconsistent in their formatting so
feel free to tweak those before commit.
On Thu, Jun 15, 2023 at 12:48 AM
From: Aaron Nyholm
---
rtemsbsd/sys/arm64/xilinx/versal_slcr.c | 34 ++---
rtemsbsd/sys/arm64/xilinx/versal_slcr.h | 6 +
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/rtemsbsd/sys/arm64/xilinx/versal_slcr.c
b/rtemsbsd/sys/arm64/xilinx/versal_slcr.c
in
On the Versal when the GEM clock is routed from a PLL in another domain
it goes through another clock divider. This check accounts for this
extra clock divider when setting the clock.
Thanks, Aaron.
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