Hello Chris,
I have currently no time to review this or follow your discussion. Please ping
me if you have something final to commit.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail
OK, thats good to hear. I have some extra code here I can incorporate
when I have time, like DMA driven I2S audio, SPI and UART.
On 19/10/2014 2:27 PM, Tomasz Gregorek wrote:
Hi Chris
Yes, there are more registers specific to specific CPU versions,
different number of UARTs and other periph
Hi Chris
2014-10-19 8:36 GMT+02:00 Chris Nott :
> Hi,
>
> On 18/10/2014 3:45 AM, Tomasz Gregorek wrote:
>
> Hi Chris
>
> - pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m /
> 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48;
>
> Your fix for the PLL_Q calculation
Hi,
On 18/10/2014 3:45 AM, Tomasz Gregorek wrote:
Hi Chris
- pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m
/ 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48;
Your fix for the PLL_Q calculation is correct.
It supposed to be rounding from <=X.5 to X and from >X
Hi Chris
- pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m /
48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48;
Your fix for the PLL_Q calculation is correct.
It supposed to be rounding from <=X.5 to X and from >X.5 to (X+1) but first
I messed up the equation second t
Hi,
I sent these header file changes previously, they didn't get picked up.
I re-merged with the head, cleaned up formatting and fixed a bug with
PLL_Q setting not generating the right auxiliary clock frequency for USB
peripheral - Tomasz this was your change, could you please review my fix.
