On Thu, Oct 13, 2022 at 2:18 AM wrote:
>
> > On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On 12/10/2022 16:36, Joel Sherrill wrote:
> > > Hi
> > >
> > > I was looking at the bsp
> On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On 12/10/2022 16:36, Joel Sherrill wrote:
> > Hi
> >
> > I was looking at the bsp default settings for sparc/leon3 to show
> > someone an
Hi Joel,
We can do like below to remove visibility of RISCV_BOOT_HARTID from
other architecture configurations and only visible to RISC-V.
Changes in spec/build/cpukits
1. Remove "optboothartid" build-dependency from "cpuotps"
2. Add the "cpuriscvhartid" to generate the "hartid.h" using "optboot
On 12/10/2022 16:36, Joel Sherrill wrote:
Hi
I was looking at the bsp default settings for sparc/leon3 to show
someone and noticed this which is out of place.
# boot hartid (processor number) of risc-v cpu (default 0)
RISCV_BOOT_HARTID = 0
I looked around and see it is an architecture specif
Hi Joel,This is relevant to my interests since I am working on a RISC-V BSP variant and I am adding a few options in the spec/build/bsps/riscv/riscv directory.Could this instance be fixed by moving it to the spec/build/bsps/riscv directory?Regards,AlanFrom: Joel SherrillSent: Wednesday, October 12,
