Re: Building RISC-V BSP

2017-06-04 Thread Joel Sherrill
On Jun 4, 2017 4:37 PM, "Hesham Almatary" wrote: Hi Denis, Yes, I'm willing to fix these, just need time. Shouldn't be that difficult. You can get more details on RISC-V assembly reading RISC-V specs (especially user-level spec) [1]. For example/references, you may have a look at the riscv-linu

Re: Building RISC-V BSP

2017-06-04 Thread Hesham Almatary
Hi Denis, Yes, I'm willing to fix these, just need time. Shouldn't be that difficult. You can get more details on RISC-V assembly reading RISC-V specs (especially user-level spec) [1]. For example/references, you may have a look at the riscv-linux and/or seL4 ports [2, 3] (though, you've to be aw

Re: Building RISC-V BSP

2017-06-04 Thread Denis Obrezkov
2017-06-05 0:14 GMT+03:00 Hesham Almatary : > Hi Denis, > > Yes, the Host-Target-Interface (HTIF) has been refactored/removed in > RISC-V. Also, it was meant to work with riscv front-end server > (riscv-fesvr) which is not the case for your HiFive BSP I guess. > > I believe now it's the good time

Re: Building RISC-V BSP

2017-06-04 Thread Hesham Almatary
Hi Denis, Yes, the Host-Target-Interface (HTIF) has been refactored/removed in RISC-V. Also, it was meant to work with riscv front-end server (riscv-fesvr) which is not the case for your HiFive BSP I guess. I believe now it's the good time for you to start creating your own HiFive BSP. You'll hav

Re: Building RISC-V BSP

2017-06-04 Thread Denis Obrezkov
2017-06-04 16:17 GMT+03:00 Denis Obrezkov : > Now I have a problem with console-io.c file. > The problem is with csr macros - there is no more such a register "tohost". > Here it is described a little: > https://github.com/riscv/riscv-pk/issues/25 > > Could you explain what should be done here and

Re: Building RISC-V BSP

2017-06-04 Thread Denis Obrezkov
Now I have a problem with console-io.c file. The problem is with csr macros - there is no more such a register "tohost". Here it is described a little: https://github.com/riscv/riscv-pk/issues/25 Could you explain what should be done here and what for was mtohost register? 2017-06-02 2:22 GMT+03:

Re: Building RISC-V BSP

2017-06-01 Thread Denis Obrezkov
So, am I understand right, that I should make my repo, submit commits to it, produce patches and send them to your repo as pool requests? And should I make my repo by cloning yours? 2017-06-02 2:02 GMT+03:00 Hesham Almatary : > Hi Denis, > > On Fri, Jun 2, 2017 at 1:27 AM, Denis Obrezkov > wrote

Re: Building RISC-V BSP

2017-06-01 Thread Denis Obrezkov
Hello Hesham, should I apply your patches? or should I paste all of them to some directory (rsb has several 'patches' folders). Also, could you describe our workflow? In the context of with what repository I should work and where I should direct my pull requests. 2017-06-01 5:09 GMT+03:00 Hesha

Re: Building RISC-V BSP

2017-05-31 Thread Hesham Almatary
Hi Denis, I submitted two patches for the tools, please use the latest only and rebuild the tools. This should avoid the newlib issues you had above as it uses main riscv patches. I'll look into the port this weekend and submit fixes unless you beat me to it. Meanwhile, you can submit error messa

Re: Building RISC-V BSP

2017-05-31 Thread Denis Obrezkov
2017-05-31 16:39 GMT+03:00 Denis Obrezkov : > Thanks, I downloaded it. > There was a mistake also that _JBLEN wasn't defined in machine/setjmp.h > I don't know the exact value, so I did the following: > #ifdef __riscv > > /* TBD: not the exact number */ > > #define _JBLEN 16 > > #endif > > Now, it

Re: Building RISC-V BSP

2017-05-31 Thread Denis Obrezkov
Thanks, I downloaded it. There was a mistake also that _JBLEN wasn't defined in machine/setjmp.h I don't know the exact value, so I did the following: #ifdef __riscv /* TBD: not the exact number */ #define _JBLEN 16 #endif Now, it compiles further. But then I get the error: riscv32-rtems4.12-gc

Re: Building RISC-V BSP

2017-05-30 Thread Hesham Almatary
Hi Denis, Please use priv-1.10 branch. I rebased it (against master) and added some fixes to make the build progress. Still, there's more work needed. Your contributions are welcomed. Cheers, Hesham . On Wed, May 31, 2017 at 6:16 AM, Hesham Almatary wrote: > Hi Denis, > > Yes, that's a leftover

Re: Building RISC-V BSP

2017-05-30 Thread Hesham Almatary
Hi Denis, Yes, that's a leftover flag that used to exist in the 2-year-old toolchain. There's no m32 (or m64) flag anymore. I submitted a fix (54bf80e) to my repo. You'll most likely get similar issues though in later stages. Fix-ups are welcome. Cheers, Hesham On Wed, May 31, 2017 at 3:19 AM, G

Re: Building RISC-V BSP

2017-05-30 Thread Gedare Bloom
On Tue, May 30, 2017 at 12:09 PM, Denis Obrezkov wrote: > 2017-05-30 18:31 GMT+03:00 Gedare Bloom : >> >> On Tue, May 30, 2017 at 7:49 AM, Denis Obrezkov >> wrote: >> > Hello, >> > I am trying to build RTEMS for RISC-V BSP. I applied Hesham's patch for >> > RSB >> > and built RSB. But when I am t

Re: Building RISC-V BSP

2017-05-30 Thread Denis Obrezkov
2017-05-30 18:31 GMT+03:00 Gedare Bloom : > On Tue, May 30, 2017 at 7:49 AM, Denis Obrezkov > wrote: > > Hello, > > I am trying to build RTEMS for RISC-V BSP. I applied Hesham's patch for > RSB > > and built RSB. But when I am trying to build rtems-generic target I get > the > > mistake. > > This

Re: Building RISC-V BSP

2017-05-30 Thread Gedare Bloom
On Tue, May 30, 2017 at 7:49 AM, Denis Obrezkov wrote: > Hello, > I am trying to build RTEMS for RISC-V BSP. I applied Hesham's patch for RSB > and built RSB. But when I am trying to build rtems-generic target I get the > mistake. > This is my sequence of steps: > > git clone git://git.rtems.org/r