I checked in this to GCC patch:
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=261619
I will back port it to GCC 7 and 8 next Friday and update the RSB to use
the latest GCC 8 branch for RISC-V.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germa
On 13/06/18 12:21, Hesham Almatary wrote:
+MULTILIB_OPTIONS +=
march=rv32i/march=rv32im/march=rv32imafd/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv64imafd/march=rv64imac/march=rv64imafdc
+MULTILIB_DIRNAMES += rv32i rv32im rv32imafd rv32iac
rv32imac
On Wed, Jun 13, 2018 at 10:39 AM, Sebastian Huber
wrote:
> Add multilib variants for -march=rv64imafd, e.g. to support the BOOMv2 core.
>
> Add -mcmodel=medany as a variant of the 64-bit multilibs for RTEMS. The
> ratinale for this change is that several existing RISC-V chips map the
> RAM at 0x8
