I should clarify that the terms SPL and MLO seem to be used
interchangeably. So I guess it's pretty much a matter of figuring out
where the internal ROM-based bootloader exactly transfers the "second
stage" bootloader from (i.e. location in memory) and to what location
in the internal SRAM to do
I should clarify that the terms SPL and MLO seem to be used
interchangeably. So I guess it's pretty much a matter of figuring out
where the internal ROM-based bootloader exactly transfers the "second
stage" bootloader from (i.e. location in memory) and to what location
in the internal SRAM to do t
I'll definitely check out the AM335x TRM.
Referring to this link
(http://beagleboard.org/project/U-Boot+%28V1%29/), it briefly
elaborates that the U-boot on the Beaglebone consists of two phases.
First phase consists of the SPL which is transferred from eMMC or uSD
(depending on boot switch) and m
On 3/26/2015 2:22 PM, Gedare Bloom wrote:
On Thu, Mar 26, 2015 at 2:18 PM, Joel Sherrill
wrote:
On 03/26/2015 11:35 AM, Jarielle Catbagan wrote:
It looks like the internal ROM-based bootloader looks for a secondary
program loader (SPL) that initializes the necessary devices to
continue the boo
On 3/26/2015 2:18 PM, Joel Sherrill wrote:
On 03/26/2015 11:35 AM, Jarielle Catbagan wrote:
It looks like the internal ROM-based bootloader looks for a secondary
program loader (SPL) that initializes the necessary devices to
continue the boot process and pass control to a third-stage
bootloader.
The lower 5 bits of the SYSBOOT pins determine the order that the ROM
bootloader
will follow when trying to boot from something external (memory or device).
Referring to the schematic (pg6), the default value of SYSBOOT[4:0] is
11100.
Referring to table 26-7 of the TRM, this corresponds to the s
Refer to chapter 26 of this document (AM335x TRM):
http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf
for more detail on the booting process of the chip.
Depending on how hard it is to reconfigure the SYSBOOT pins, it may be
simpler to initially try to boot this off the UART. Then once that works,
i
On Thu, Mar 26, 2015 at 2:18 PM, Joel Sherrill
wrote:
> On 03/26/2015 11:35 AM, Jarielle Catbagan wrote:
>>
>> It looks like the internal ROM-based bootloader looks for a secondary
>> program loader (SPL) that initializes the necessary devices to
>> continue the boot process and pass control to a
Right...
I'm catching up on this CPU, I've done a bit more of this on the iMX6,
but it appears
to be quite similar...
Referring to the schematic here:
https://github.com/CircuitCo/BeagleBone-Black/blob/master/BBB_SCH.pdf?raw=true
When the CPU first starts out of a cold reset, it will execute c
On 03/26/2015 11:35 AM, Jarielle Catbagan wrote:
It looks like the internal ROM-based bootloader looks for a secondary
program loader (SPL) that initializes the necessary devices to
continue the boot process and pass control to a third-stage
bootloader. So now I believe it's a matter of finding
It looks like the internal ROM-based bootloader looks for a secondary
program loader (SPL) that initializes the necessary devices to
continue the boot process and pass control to a third-stage
bootloader. So now I believe it's a matter of finding whether there
are existing code implementations of
To put things into context in regards to the conversation that I was
having with Ed, Dr. Joel, and Gedare:
I am currently in the process of looking into porting MicroMonitor to
the Beaglebone Black. As indicated by Ed, "[t]he difficulty of the
port will depend on how much existing CPU-initializat
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