Re: CVA6 RISC-V support

Hello, Thanks for sending out the patches. Could you please send them as emails instead of attachments? e.g., using git send-email [1]. That'll be easier to review and comment on. [1] https://docs.rtems.org/branches/master/user/support/contrib.html Regards, Hesham On Tue, 1 Aug 2023 at 16:53, E

RE: CVA6 RISC-V support

SMP should be independent. De : Joel Sherrill Envoyé : mardi 1 août 2023 20:54 À : EYSSARTIER Kevin Cc : devel@rtems.org Objet : Re: CVA6 RISC-V support Thanks for the submission. It's a bit hard to review with the patches as attachments rather than having been sent via git send-email but

Re: CVA6 RISC-V support

Thanks for the submission. It's a bit hard to review with the patches as attachments rather than having been sent via git send-email but here goes. Hopefully someone with more RISC-V knowledge can comment also. 0001 - long comment appears to be one line. Please break into multiple lines. 0001 -

CVA6 RISC-V support

Classified as: {THALES GROUP LIMITED DISTRIBUTION} Hello, I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V CVA6 processor GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux Th