Re: ARM cp15 c1 control on the BBB at _start

2018-03-06 Thread Chris Johns
On 6/3/18 6:40 pm, Sebastian Huber wrote: > On 05/03/18 23:12, Chris Johns wrote: >> Note, the Zynq does not clear the A flag in it's specific MMU set up call so >> does it assume the boot loader will clear it? >> >> Why not clear the A flag and remove any restrictions and try and make the >> BSPs

Re: ARM cp15 c1 control on the BBB at _start

2018-03-05 Thread Sebastian Huber
On 05/03/18 23:12, Chris Johns wrote: Note, the Zynq does not clear the A flag in it's specific MMU set up call so does it assume the boot loader will clear it? Why not clear the A flag and remove any restrictions and try and make the BSPs consistent? A set SCTLR[A] bit after initialization (i

ARM cp15 c1 control on the BBB at _start

2018-03-05 Thread Chris Johns
Hi, I have a recent git master build of OpenOCD loading an RTEMS executable and it runs without error until `bsp_reset` where it stops on a break point. I however cannot step cleanly if I set a break point on `Init` and I am looking into this. To start with I am looking at the MMU and cache set up