Alex,
How do you handle single or dual GPIO channel configurations?
How do you handle 1 to 32 GPIO pins?
On 17/3/2022 3:25 am, Alex White wrote:
> On Wed, Mar 16, 2022 at 10:27 AM Gedare Bloom wrote:
>>
>> On Tue, Mar 15, 2022 at 2:28 PM Alex White wrote:
>>>
>>> ---
>>> bsps/include/dev/gpio
On Wed, Mar 16, 2022 at 10:25 AM Alex White wrote:
>
> On Wed, Mar 16, 2022 at 10:27 AM Gedare Bloom wrote:
> >
> > On Tue, Mar 15, 2022 at 2:28 PM Alex White wrote:
> > >
> > > ---
> > > bsps/include/dev/gpio/xilinx-axi-gpio.h | 311 ++
> > > bsps/shared/dev/gpio/xilinx-a
On Wed, Mar 16, 2022 at 10:27 AM Gedare Bloom wrote:
>
> On Tue, Mar 15, 2022 at 2:28 PM Alex White wrote:
> >
> > ---
> > bsps/include/dev/gpio/xilinx-axi-gpio.h | 311 ++
> > bsps/shared/dev/gpio/xilinx-axi-gpio.c | 221 +
>
> Is this AXI GPIO interface
On Tue, Mar 15, 2022 at 2:28 PM Alex White wrote:
>
> ---
> bsps/include/dev/gpio/xilinx-axi-gpio.h | 311 ++
> bsps/shared/dev/gpio/xilinx-axi-gpio.c| 221 +
Is this AXI GPIO interface consistent across Xilinx IP?
> .../bsps/microblaze/microblaze_fpga/
Hello Alex,
maybe someone from OAR should step in as a microblaze maintainer.
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---
bsps/include/dev/gpio/xilinx-axi-gpio.h | 311 ++
bsps/shared/dev/gpio/xilinx-axi-gpio.c| 221 +
.../bsps/microblaze/microblaze_fpga/obj.yml | 2 +
3 files changed, 534 insertions(+)
create mode 100644 bsps/include/dev/gpio/xilinx-axi-gpio.h
crea
