Re: [PATCH] riscv/console: console-config.c update

I am not sure if > DTS allows having something like /soc/serial@ in the stdout-path. > Thanks for the suggestion Hesham. We are discussing internally whether to go with a variant of the existing riscv BSP or introduce a new riscv BSP altogether. > On Tue, 18 May 2021 at 20:43, Sebastian

Fwd: [PATCH] riscv/console: console-config.c update

Gentle Reminder. Hi All, Can you please review this patch and let me know if there are any suggestions/comments. Regards, Somesh -- Forwarded message - From: Somesh Deshmukh Date: Wed, May 5, 2021 at 11:26 PM Subject: [PATCH] riscv/console: console-config.c update To: Cc

[PATCH] riscv/console: console-config.c update

- Parsing the sub-node should be available generic not specific to Freedom Arty310 board. If we remove the Freedom Arty macro now, it will lose backward compatibility.The proposed change will retain the backward compatibility and also adds the necessary fix for parsing sub-node. --- bsps/ris

Re: [PATCH] riscv/start: Startup sequence update.

On Mon, May 3, 2021 at 5:36 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 03/05/2021 13:47, somesh deshmukh wrote: > > > I performed the following sequence of instruction: > > ./waf clean > > ./waf configure > > ./waf > > > >

Re: [PATCH] riscv/start: Startup sequence update.

On Mon, May 3, 2021 at 5:01 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 03/05/2021 13:25, somesh deshmukh wrote: > > > > > I tried this patch with the master branch and the build is failing > > after applying the patch. > > > > T

Re: [PATCH] riscv/start: Startup sequence update.

Hi Sebastian, I tried this patch with the master branch and the build is failing after applying the patch. The error message includes: /home/somesh/Documents/rtems-temp/rtems/6/lib/gcc/riscv-rtems6/10.2.1/../../../../riscv-rtems6/bin/ld: /home/somesh/work/rtems-master/rtems/build/riscv/rv64imafd

Re: [PATCH] riscv/start: Startup sequence update.

Hi Sebastian, For testing, I had manually added the device tree blob address into the a1 register. On Fri, Apr 30, 2021 at 6:52 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 29/04/2021 20:53, Sebastian Huber wrote: > > > On 29/04/2021 20:18, Hesham Almatary wrote: > > > >>

[PATCH] riscv/console: console-config.c update

- Parsing the sub-node should be available generic not specific to Freedom Arty310 board. If we remove the Freedom Arty macro now, it will lose backward compatibility.The proposed change will retain the backward compatibility and also adds the necessary fix for parsing sub-node. - Restored n

Re: [PATCH] riscv/console: Updated the console-config.c file

On Thu, Apr 29, 2021 at 10:59 PM Hesham Almatary < hesham.almat...@cl.cam.ac.uk> wrote: > On Wed, 28 Apr 2021 at 15:23, Somesh Deshmukh > wrote: > > > > - Parsing the sub-node should be available generic not specific to > Freedom > > Arty310 board. If we remo

[PATCH] riscv/start: Startup sequence update.

- The current startup sequence performs the call to the bsp_fdt_copy() and then performs memset to the BSS region. In bsp_fdt_copy(), RTEMS allocates memory for bsp_fdt_blob into BSS region which is yet to initialize. With current startup sequence, the bsp_fdt_blob is getting erased after mem

[PATCH] riscv/console: Updated the console-config.c file

- Parsing the sub-node should be available generic not specific to Freedom Arty310 board. If we remove the Freedom Arty macro now, it will lose backward compatibility.The proposed change will retain the backward compatibility and also adds the necessary fix for parsing sub-node. - Line 234 a

Re: RTEMS on PolarFire SoC ICICLE Kit FPGA

Hi Hesham, Comments added below and please find the attached device tree source file. Regards, Somesh On Sun, Apr 25, 2021 at 12:34 AM Hesham Almatary < hesham.almat...@cl.cam.ac.uk> wrote: > Hello Somesh, > > On Sat, 24 Apr 2021 at 20:52, somesh deshmukh > wrote: > >

Re: RTEMS on PolarFire SoC ICICLE Kit FPGA

uide > on this. > > On Thu, Apr 22, 2021, 10:52 PM somesh deshmukh > wrote: > >> I was able to test the rtems hello-world example and ticker example on >> the polarfire soc icicle kit. >> >> A little background about Polarfire SoC ICICLE Kit. >> The Pola

RTEMS on PolarFire SoC ICICLE Kit FPGA

I was able to test the rtems hello-world example and ticker example on the polarfire soc icicle kit. A little background about Polarfire SoC ICICLE Kit. The PolarFire SoC Icicle kit is a low-cost development platform that enables the evaluation of the five-core Linux capable RISC-V microprocessor

Re: RTEMS booting on PolarFire SoC FPGA

expects the bootloader to pass the HARTID in a0, and the FDT pointer > in a1. > > > On Tue, 5 Jan 2021 at 13:16, somesh deshmukh > wrote: > > > > Hi All, > > I am trying to boot RTEMS on PolarFire SoC FPGA using rv64imafdc_medany > BSP. > > I am using a s

RTEMS booting on PolarFire SoC FPGA

Hi All, I am trying to boot RTEMS on PolarFire SoC FPGA using rv64imafdc_medany BSP. I am using a simple bare-metal bootloader application to copy the hello.bin(I generated a hello.bin file from hello.exe from testsuits/samples directory) at the address 0x8000. Attached is the disassembly of th

Booting issue with rv64imafd_medany on hardware

Hi All, I am testing my custom RISC-V rv64imafd_medany BSP on hardware. I have created a launch configuration for Eclipse-based IDE with a simple hello world application .elf file. After launching the application the control is stuck at 0x8000 address which is the start address and the instruc

Re: New BSP development for Microchip's RISC-V based PolarFire SoC ICICLE Kit

Hi Sebastian, I also wanted to add the HAL APIs to the BSP which will perform the basic initializations and memory configuration. I missed this point in the last mail. Regards, Somesh On Tue, Nov 10, 2020 at 12:59 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello Somesh, >

New BSP development for Microchip's RISC-V based PolarFire SoC ICICLE Kit

Hi All, I am trying to port the RTEMS v5.1 on PolarFire SoC ICICLE Kit. The available console driver in the risc-v bsp does not support the target hardware so I am looking into developing a custom BSP for the PolarFire SoC ICICLE Kit. It will be a great help if anyone could point me to custom BSP