[PATCH rtems-docs] user/riscv/sifive_u: Added Documentation for the new SiFive Unleashed BSP

This commit contains all the required information to build and run the new BSP. --- user/bsps/bsps-riscv.rst | 52 1 file changed, 52 insertions(+) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 263796e..76b70ce 100644 --- a/user/bs

[PATCH] bsp/riscv: Add a new SiFive Unleashed QEMU bsp

++ b/spec/build/bsps/riscv/riscv/bspsifive_u.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: riscv +bsp: sifive_u +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2023 Amna Mannan +cppflags: [] +enabled-by: true +family: riscv +includes: [] +install: []

GSOC Proposal - SiFive HiFive Unleashed RISC-V port for RTEMS

Hello everyone, I'm Amna Mannan, wanted to share my proposal for this year with you. I'll be to glad to know more about this proposal. I have updated the GSOC 2023 wiki. Here's a link to my proposal. https://docs.google.com/document/d/1-RfydFwHBI5dvJKJu9TLpVI9wmVRcrqcTuHLJGBNTME/e