On 16.04.24 16:51, Kinsey Moore wrote:
This adds warnings for arm_interrupt_enable_interrupts and
arm_interrupt_restore_interrupts. I suspect a missing header. They also
generate a link error on the a53_lp64_qemu bsp. I also dislike the
while(true), but I don't think we officially have anything
This adds warnings for arm_interrupt_enable_interrupts and
arm_interrupt_restore_interrupts. I suspect a missing header. They also
generate a link error on the a53_lp64_qemu bsp. I also dislike the
while(true), but I don't think we officially have anything against it and
there are existing examples
The clock from the ARM timer is derived from the system clock. This clock can
change dynamically e.g. if the system goes into reduced power or in low power
mode. Thus the clock speed adapts to the overall system performance
capabilities. For accurate timing it is recommended to use the system ti
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
---
bsps/sh
Hi,
it seems there is a bug in rtems_gpio_bsp_clear; mmio_set reads back the
GPIO_DATAOUT register, so other active gpios are cleared too.
To clear a bit its necessary to use mmio_write.
---
bsps/arm/beagle/gpio/bbb-gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bs
---
bsps/powerpc/qoriq/irq/irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/bsps/powerpc/qoriq/irq/irq.c b/bsps/powerpc/qoriq/irq/irq.c
index 2a5e3e9a75..96fbe4e020 100644
--- a/bsps/powerpc/qoriq/irq/irq.c
+++ b/bsps/powerpc/qoriq/irq/irq.c
@@ -47,6 +47,7 @@
#include
#include
#inclu
