On 21/09/2021 02:15, Gedare Bloom wrote:
looks good, thanks. I'll follow-up later as I make progress on the
versal smp side too. that's still a bit broken.
On Mon, Sep 20, 2021 at 4:56 PM Kinsey Moore wrote:
Version 1 of this patch did not update the Versal BSP's usage of the MMU
calls.
The
On 20/09/2021 23:38, Kinsey Moore wrote:
The order in which step checks for 1 and 2 are not rigidly defined and
may actually occur in either order depending on how the threads execute.
This waits for the job to complete to enforce the existing ordering.
---
testsuites/smptests/smpmulticast01/in
From: Chris Johns
- These calls clash with the Linux IO header in LibBSD. Making these
conditional here means BSPs build and the imported Linux header is
untouched.
Updates #4245
---
bsps/powerpc/include/libcpu/io.h | 8
1 file changed, 8 insertions(+)
diff --git a/bsps/powerpc/in
From: Chris Johns
Closes #4516
---
bsps/powerpc/motorola_powerpc/include/bsp.h | 34 +++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h
b/bsps/powerpc/motorola_powerpc/include/bsp.h
index 62e740272a..7d362bf406 100644
printk(" EAX = 0%08" PRIx32 "EBX = 0%08" PRIx32 "ECX = 0%08"
PRIx32 "EDX = 0%08" PRIx32 "\n",
should it look like this gedare? will send once you give the ok
On Sun, 19 Sept 2021 at 17:42, zack leung wrote:
> Bumo
>
> Il ven 17 set 2021, 19:57 zack leung ha
> scritto:
>
>> Where
From: Chris Johns
- Add the dc net dev to the BSP
- Add the ukphy support
- Add PCI Legacy bus support to the PowerPC
Closes #4514
---
freebsd/sys/dev/dc/if_dc.c | 7 +++
freebsd/sys/dev/dc/if_dcreg.h | 7 +++
libbsd.py
From: Chris Johns
- Add PCI IO region support
- Add support map buffers to PCI address space
- Add BSP conditional IO space support. Some PC implementations
have PCI IO space mapped differently to memory space and this needs
to be reflected in the busspace.
- Include bsp.h to pick per BSP
looks good, thanks. I'll follow-up later as I make progress on the
versal smp side too. that's still a bit broken.
On Mon, Sep 20, 2021 at 4:56 PM Kinsey Moore wrote:
>
> Version 1 of this patch did not update the Versal BSP's usage of the MMU
> calls.
>
>
> Kinsey
>
> On 9/20/2021 17:43, Kinsey
Version 1 of this patch did not update the Versal BSP's usage of the MMU
calls.
Kinsey
On 9/20/2021 17:43, Kinsey Moore wrote:
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
bsps/aarch64/shared/start/start.S | 12 +--
.../aarch64/xilinx-versal/start/bspstartm
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
bsps/aarch64/shared/start/start.S | 12 +--
bsps/aarch64/xilinx-zynqmp/include/bsp.h
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
---
.../shared/dev/irq/arm-gicv2-get-attributes.c | 77 +++
bsps/share
GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only
configured for 192 interrupts.
---
bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
b/bsps/aarch64/xilinx-zynqmp/includ
The order in which step checks for 1 and 2 are not rigidly defined and
may actually occur in either order depending on how the threads execute.
This waits for the job to complete to enforce the existing ordering.
---
testsuites/smptests/smpmulticast01/init.c | 1 +
1 file changed, 1 insertion(+)
This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on
Hi Alex,
I prefer Python’s argparse and prefer we move the other way. The options
handling originally came from the RSB and has lots of issues. I regret it.
Sorry about this.
Chris
> On 21 Sep 2021, at 2:08 am, Alex White wrote:
>
> This changes the object holding the command line argumen
On Mon, Sep 13, 2021 at 5:44 PM Joel Sherrill wrote:
>
> On Sun, Sep 12, 2021 at 7:02 PM zack leung wrote:
> >
> > Thread id is now a Hex value.
> > Updates #4203
> > ---
> > cpukit/score/cpu/i386/cpu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/cpukit/score/cpu
This changes the object holding the command line arguments from an
argparse.Namespace to an rtemstoolkit.options.command_line. This matches
the type expected by rtemstoolkit.mailer.mail.__init__ and is the type
used in tester/rt/test.py and run.py.
---
tester/rt/check.py | 151
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