Re: [PATCH] user: Split the ARM BSPs source into separate files.

On 15/6/19 10:24 am, Gedare Bloom wrote: > Sorry to top post: just to be clear, names will be like > user/bsps/arm/altera-cyclone-v.rst and similar? That will be a good change. > Glad > to see this documentation happening! Sure. I am fine with this. I will post a v2 patch for review. Chris _

Re: [PATCH] user: Split the ARM BSPs source into separate files.

Sorry to top post: just to be clear, names will be like user/bsps/arm/altera-cyclone-v.rst and similar? That will be a good change. Glad to see this documentation happening! On Fri, Jun 14, 2019, 6:14 PM Chris Johns wrote: > On 14/6/19 10:05 pm, Joel Sherrill wrote: > > On Fri, Jun 14, 2019, 3:4

Re: [PATCH] user: Split the ARM BSPs source into separate files.

On 14/6/19 10:05 pm, Joel Sherrill wrote: > On Fri, Jun 14, 2019, 3:48 AM Sebastian Huber > > > wrote: > On 14/06/2019 08:42, chr...@rtems.org wrote: > > From: Chris Johnsmailto:chr...@rtems.org>> > > > > --- >

Re: [RSB PATCH 0/2] Add standalone SIS as build target

On 15/6/19 8:00 am, Jiri Gaisler wrote: > Two patches to add standalone SIS as bare target, and to build it for > SPARC and RISC-V tool-chains. Look good. Please check in. Thank you for this. Chris ___ devel mailing list devel@rtems.org http://lists.rt

[RSB PATCH 1/2] Add bare target to build standalone sis (devel/sis)

--- bare/config/devel/sis-2-1.cfg | 18 + bare/config/devel/sis.bset| 8 source-builder/config/sis-2-1.cfg | 66 +++ 3 files changed, 92 insertions(+) create mode 100644 bare/config/devel/sis-2-1.cfg create mode 100644 bare/config/devel/sis.b

[RSB PATCH 0/2] Add standalone SIS as build target

Two patches to add standalone SIS as bare target, and to build it for SPARC and RISC-V tool-chains. Jiri Gaisler (2): Add bare target to build standalone sis (devel/sis) Build standalone sis for SPARC and RISC-V targets bare/config/devel/sis-2-1.cfg | 18 + bare/config/devel/sis

[RSB PATCH 2/2] Build standalone sis for SPARC and RISC-V targets

--- rtems/config/5/rtems-riscv.bset | 1 + rtems/config/5/rtems-sparc.bset | 2 ++ 2 files changed, 3 insertions(+) diff --git a/rtems/config/5/rtems-riscv.bset b/rtems/config/5/rtems-riscv.bset index 99f0754..6e9de99 100644 --- a/rtems/config/5/rtems-riscv.bset +++ b/rtems/config/5/rtems-riscv.b

Fwd: FYI about top-level config change

Hi Others probably saw this but it looks like the kind of change which might break builds so I thought I would forward it. --joel -- Forwarded message - From: Tom Tromey Date: Fri, Jun 14, 2019, 2:26 PM Subject: FYI about top-level config change To: Binutils Development Hi.

Re: [PATCH] user: Split the ARM BSPs source into separate files.

On Fri, Jun 14, 2019, 3:48 AM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 14/06/2019 08:42, chr...@rtems.org wrote: > > From: Chris Johns > > > > --- > > user/bsps/bsp-altera-cyclone-v.rst | 83 ++ > > I would name them bsp-arm-altera-cyclone-v.rst, etc. > Also could p

Re: [PATCH] CTF TSDL

Hello Ravindra, could you please add some comments which explain the magic numbers, e.g. 1421703448 and the relationship to the raw event recording items (rtems_record_item) and data which is already somehow converted by the client. -- Sebastian Huber, embedded brains GmbH Address : Dornier

[PATCH] CTF TSDL

--- misc/CTF/record-ctf.ref | 54 + 1 file changed, 54 insertions(+) create mode 100644 misc/CTF/record-ctf.ref diff --git a/misc/CTF/record-ctf.ref b/misc/CTF/record-ctf.ref new file mode 100644 index 000..a27757c --- /dev/null +++ b/misc/CTF/

Re: [PATCH] user: Split the ARM BSPs source into separate files.

On 14/06/2019 08:42, chr...@rtems.org wrote: From: Chris Johns --- user/bsps/bsp-altera-cyclone-v.rst | 83 ++ I would name them bsp-arm-altera-cyclone-v.rst, etc. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16