Potential SIS or RTEMS/libbsd problem

2019-05-21 Thread Sebastian Huber
Hello, in the libbsd there is a test for the Epoch Based Reclamation: https://git.rtems.org/rtems-libbsd/tree/testsuite/epoch01/test_main.c When I run this test using the leon3 BSP on real hardware (150MHz NGMP FP) the test completes successfully. If I run the test on the SIS, it is stuck at

Re: SMP Testing of RISC-V

2019-05-21 Thread Sebastian Huber
On 21/05/2019 16:26, Joel Sherrill wrote: On Mon, May 20, 2019 at 11:23 PM Sebastian Huber > wrote: On 20/05/2019 20:23, Joel Sherrill wrote: > Hi > > I can't seem to find the number of cores the RISC-V port has been tested >

[PATCH] score: Compact objects class indices

2019-05-21 Thread Sebastian Huber
--- cpukit/include/rtems/score/objectdata.h | 48 +++-- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/cpukit/include/rtems/score/objectdata.h b/cpukit/include/rtems/score/objectdata.h index ce6e3c63a4..a33f9d497f 100644 --- a/cpukit/include/rtems/scor

Re: GSoC Project | Basic Support for Trace Compass

2019-05-21 Thread Sebastian Huber
On 21/05/2019 20:21, Ravindra Kumar Meena wrote: Hi Sebastian, I followed https://diamon.org/ctf/ and tried to code. Which code did you try? Did you have a look at babeltrace? https://diamon.org/babeltrace/ I would start with this if I had to convert an arbitrary format to CTF. I forked t

Re: Odd Formatting in CPU Supplement

2019-05-21 Thread Sebastian Huber
On 21/05/2019 15:29, Joel Sherrill wrote: On Mon, May 20, 2019 at 11:19 PM Sebastian Huber > wrote: Hello Joel, it is in line what GCC prints: riscv-rtems5-gcc -print-multi-lib .; rv32i/ilp32;@march=rv32i@mabi=ilp32 rv32im/

Renaming examples-v2 to rtems-examples.

2019-05-21 Thread Chris Johns
Hi, The examples-v2 repo's name should be rtems-examples. I would like to make this change. It will require a local repo edit of the URL to point to the new name. Comments? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/lis

Re: GSoC Project | Basic Support for Trace Compass

2019-05-21 Thread Ravindra Kumar Meena
Hi Sebastian, I followed https://diamon.org/ctf/ and tried to code. I forked the rtems-tools and made a commit. https://github.com/rmeena840/rtems-tools/commit/e1917f5afeba051e4e87285eed9e36b2591dc643 Please have a look and let me know if I am going in the right direction. I would like to ask o

Re: [PATCH] posix: Remove unused OBJECTS_POSIX_INTERRUPTS

2019-05-21 Thread Joel Sherrill
On Mon, May 20, 2019 at 1:31 AM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 17/05/2019 21:38, Joel Sherrill wrote: > > > > I assume you intentionally left the gap in numbering of POSIX API > > classes for historical consistency. But it does leave a gap in the > > _Objects_Inf

Re: SMP Testing of RISC-V

2019-05-21 Thread Joel Sherrill
On Mon, May 20, 2019 at 11:23 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 20/05/2019 20:23, Joel Sherrill wrote: > > Hi > > > > I can't seem to find the number of cores the RISC-V port has been tested > > on. I couldn't even find test results for riscv RTEMS in the archive

Re: Odd Formatting in CPU Supplement

2019-05-21 Thread Joel Sherrill
On Mon, May 20, 2019 at 11:19 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello Joel, > > it is in line what GCC prints: > > riscv-rtems5-gcc -print-multi-lib > .; > rv32i/ilp32;@march=rv32i@mabi=ilp32 > rv32im/ilp32;@march=rv32im@mabi=ilp32 > rv32imafd/ilp32d;@march=rv32imaf