Hello Gedare,
On Friday 15 of July 2016 19:22:17 Gedare Bloom wrote:
> >
> > cpukit/score/include/rtems/score/percpu.h
> >
> > typedef enum {
> > /**
> >* @brief Index for relative per-CPU watchdog header.
> >*
> >* The reference time point for this header is current ticks value
> >
From: Pavel Pisa
Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it
From: Pavel Pisa
This fix strange behavior where some stale content has been
stored in level 2 cache before RTEMS has been start from U-boot
which has reappeared after MMU enable and shadow vector
table at start of SDRAM.
---
c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c | 14 +++-
From: Pavel Pisa
Memory content changes caused by relocation has to be
propagated to memory/cache level which is used/snooped
during instruction cache fill.
---
cpukit/libdl/rtl-elf.c | 3 +++
cpukit/libdl/rtl-obj.c | 67 --
cpukit/libdl/rtl-obj.h
From: Pavel Pisa
Signed-off-by: Pavel Pisa
---
c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 35 ++
1 file changed, 2 insertions(+), 33 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
b/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
index 0bec0c2..a
From: Pavel Pisa
Enable even the first megabyte of SDRAM to be cache-able after
problems with stale cache content has been resolved by previous commit.
Because major part of application usually fits to the first
megabyte this speedups test dhrystone application by factor 40.
---
.../arm/raspberr
From: Pavel Pisa
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended
From: Pavel Pisa
The changes correct libdl operation on targets which do not snoop
data change during instruction cache fill.
Text section/the first 1 MB of data has been noncacheable
after VideoCore support inclusion. Enabling cache of this
area has revealed problem with stalled data left by lo
Hello Deval Shah,
there are more ways how U-boot can be configured.
You can experiment from serial console the first.
When you see "Hit any key to stop autoboot:", send
enter for example to U-boot. Then you can start
USB and scan for ethernet
usb start
You should see
U-Boot> usb start
startin
From: Punit Vara
. added a README to pwm
. added select_pwmss() to select pwmss-generic registers, as opposed
to PWM-specific registers
. added pwmss_clock_en_status() and pwmss_tb_clock_check()
. other API improvements
. style improvements
---
c
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