LibBSD configuration and initialisation.

Hello, The following is the current status for LibBSD configuration and initialisation. I am starting to formalise the way this is done and as a result I would like any further work on LibBSD to support the configuration and initialisation methods I present. User manual document is coming.

Re: Strong APA Scheduler Implementation

Hello Darshit, On 29/06/16 11:56, Darshit Shah wrote: Hi, For the strong APA scheduler, I have added support for storing affinity sets to the Thread node structure. This code was mostly borrowed from the existing code in the priority affinity SMP scheduler. Currently, it was copied, but it s

Re: [PATCH] rtems: ensure that rtems_cache_aligned_malloc do not align less than to CPU_CACHE_LINE_BYTES.

Hello Sebastian, On Wednesday 29 of June 2016 07:28:46 Sebastian Huber wrote: > Hallo Pavel, > > On 25/06/16 17:06, Pavel Pisa wrote: > > There are architectures (for example some/many ARM Cortex-A) which have > > different cache line sizes for data and instruction caches. > > CPU kit and even BSP

Strong APA Scheduler Implementation

Hi, For the strong APA scheduler, I have added support for storing affinity sets to the Thread node structure. This code was mostly borrowed from the existing code in the priority affinity SMP scheduler. Currently, it was copied, but it should be possible to simply reuse the entire code as we