Hallo Pavel,
On 25/06/16 17:06, Pavel Pisa wrote:
There are architectures (for example some/many ARM Cortex-A) which have
different cache line sizes for data and instruction caches.
CPU kit and even BSP can be build for group of CPUs which differs
in cache line sizes as well and there are situat
Hello Mudit and others,
On Monday 27 of June 2016 15:09:39 Mudit Jain wrote:
> Hi,
>
> Any consensus regarding the issue ?
> Do we go forward with the present implementation or a change is required ?
I have pushed your patch to move development forward.
I have run RTEMS uncrustify on VideoCore so
