Ok great. Yes it was gsoc and the commit mentions it.
On Jul 14, 2014 8:10 PM, "Joel Sherrill" wrote:
>
> On Jul 14, 2014 12:27 PM, Ben Gras wrote:
> >
> > Dear all,
> >
> > I'm pretty close to be able to submit an initial version of the Beagle*
> bsp. I'm doing last-minute testing and commit cl
Sorry about that. I was building with debug on and didn’t see that error.
It is fixed in the tree now.
From: devel [mailto:devel-boun...@rtems.org] On Behalf Of Joel Sherrill
Sent: Saturday, July 12, 2014 11:14 AM
To: Ben Gras
Cc: RTEMS Devel
Subject: Re: [PATCH] capture01 build broken?
On a lo
On Jul 14, 2014 12:27 PM, Ben Gras wrote:
>
> Dear all,
>
> I'm pretty close to be able to submit an initial version of the Beagle* bsp.
> I'm doing last-minute testing and commit cleanup and that's going really well.
>
> It is technically based on Claas Ziemke's GSOC BSP for the Beagleboard. Lo
Dear all,
I'm pretty close to be able to submit an initial version of the Beagle*
bsp. I'm doing last-minute testing and commit cleanup and that's going
really well.
It is technically based on Claas Ziemke's GSOC BSP for the Beagleboard.
Long story short, I rebased it and started hacking on it.
Added commment on why I'm using BSP_fatal_exit instead of bsp_fatal
and that it is required to flush the instruction cache also in
single processor configuration.
Rewrote cache manager so that it announces the operation and then
releases the lock to avoid deadlocks.
Added test program that invoke
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the i
Invokes SMP cache management routines under different scenarios.
---
testsuites/smptests/Makefile.am |1 +
testsuites/smptests/configure.ac |1 +
testsuites/smptests/smpcache01/Makefile.am| 19 ++
testsuites/smptests/smpcache01/init.c | 291 +++
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache ju
Check that data cache snooping exists and is enabled on all cores.
---
c/src/lib/libbsp/shared/include/fatal.h |2 ++
c/src/lib/libbsp/sparc/leon3/include/leon.h | 10 ++
c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 14 --
3 files changed, 24 insertions(+), 2
Hi,
When the first time executing such a command "dlo libxx.ra:yy.rap" or "dlo
libxx.a:yy.o", RTL complains "no format loader found". when executing the
command the second time, the archive files can be loaded correctly. It is
because cache flush uses `file_size = -1` while file_size is unsigned t
10 matches
Mail list logo
