I think instruction cache operations scoped by processors make no sense on SMP.
Every processor should have the same view to the instruction memory.
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Sebastian Huber, embedded brains GmbH
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I had a closer look at the change, and it makes no sense. If you look at
void _SMP_Send_message( uint32_t cpu_index, unsigned long message )
{
Per_CPU_Control *cpu = _Per_CPU_Get_by_index( cpu_index );
_Atomic_Fetch_or_ulong( &cpu->message, message, ATOMIC_ORDER_RELAXED );
_CPU_SMP_Send_
On 2014-07-04 17:12, Daniel Cederman wrote:
> This limits the API to the default cpu_set_t. Other routines like
> pthread_setaffinity_np() don't have this limitation.
I looked at pthread_setaffinity_np() and got a bit confused. I see that it
takes both a pointer to a cpu_set_t and the size of
