This was dependent on https://github.com/apache/tvm/pull/15836, so re-trying
now to see if CI works this time.
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I'm back from holiday and want to get this RFC moving again! Thanks for all the
good discussion so far, I've made some changes to the RFC:
* Use `vscale` directly instead of `vfactor` and use TIR intrinsic to represent
`vscale` instead of introducing new node
* Opt for predication instead of clea
Sorry for the delay... What I'm aiming at is to be able to lower the TIR to a
generic CPU, that is to an architecture that does not support SVE. The TIR
will need to have some default lowering in CodeGenLLVM/CodeGenCPU, so being
able to do that is important. For that, we should be able to ass
> What I'm aiming at is to be able to lower the TIR to a generic CPU, that is
> to an architecture that does not support SVE. The TIR will need to have some
> default lowering in CodeGenLLVM/CodeGenCPU, so being able to do that is
> important.
Could it instead be in a target-dependent lowering
> Could it instead be in a target-dependent lowering pass?
Sure. My idea is to have a single SVE-aware vectorization pass in TVM, and
then be able to utilize it for all targets. I'm particularly interested in
predication. How the codegen is done doesn't matter much.
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