1. while it is true that tensor is the bottleneck, the high level code dictate
what tensor will get computed. For example, you can do dead code elimination to
remove unnecessary tensor operation(this is a real need rn), or
deforestation(which require an effect analysis) to make tensor operation
Hi @MarisaKirisame , I have several questions during the learning of AAM, about
the advantage of implementing AAM over using the normal Dataflow Analysis
framework (like the proposed one above) in the context of Relay. Because I have
no experience in Relay at all, I would appreciate it if you ca
@DKXXXL the variables/globalvariables/typevariables are free to be shared -
variables are compared by pointer equality, so each new variable is distinct.
however, nothing else in ANF mode are sharable.
I only know that using the pointer is the canonical way in RelayIR. I am not
sure about the lo
@MarisaKirisame : I might still be a little confused about the semantic and
**internal memory representation** of RelayIR. I would appreciated if you can
enlighten me: in the official document, the picture for ANF is still a DAG (a
child can have several different parent) with respect to **inte
@DKXXXL The dag idea only make sense for purely functional code. This is why we
provide ANF to transform from dag to tree, and Feature Manager to detect if it
is dag. Pointer is a good representation of location in the program and is used
that way.
--
You are receiving this because you are sub
Hi @MarisaKirisame , I currently have a question about representing "location
inside the program" because when the users want to query about the
Dataflow-Info, they will need to use "location".
**TLDR**: Pointers to ASTNodes are not one-to-one correspondent to "locations
in the program". Can th
I am thinking of Abstracting Abstract Machine. Relay has a very simple semantic
so it wont be the problem (the problem is Abstracting Abstract Machine itself).
If it is ever done, we can expose a dataflow-analysis like interface. A user
might get away with only defining the base lattice to conta
Hi @MarisaKirisame , thanks for commenting!
So which one are you looking for? ADI or AAM?
I am not familiar with either, but I remember AAM requires a state machine
transition definition of the semantics, where ADI requires a definitional
interpreter to define the semantics.
My another question
@kaitingwang are you planning on working on it btw?
--
You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
https://github.com/apache/incubator-tvm/issues/4468#issuecomment-565254638
I have talked to a professor doing program analysis, and he tell me aam > adi.
so yeah, basically I am looking at the direction of generic abstract
interpretation framework. However, I do not have time to pull this off, even
though I had wanted to do so for a long time :(
--
You are receiving
@gussmith23 @jroesch Comments appreciated!
--
You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
https://github.com/apache/incubator-tvm/issues/4468#issuecomment-565238659
@MarisaKirisame : I have some thoughts regarding your suggestion to the
possibility of a merged program analysis framework between RelayIR and HalideIR
between issue [3895](https://github.com/apache/incubator-tvm/issues/3895) and
this current issue. I found @DKXXXL 's proposal here clean and i
We will still keep variations of functions in the unified IR, which means
tensor level loop nesting might needs its own analysis.
Let us focus on discussing what is a good design for related tensor-level
dataflow analysis. Note that we do want to make sure reuse the common
infrastructures such
@tqchen, what's your suggestion? IMO, low level IR has been there for a while,
and we've had experience and understanding in low level ir. the post of unified
ir to me is just a high level proposal, details needs to be discussed further,
such as,
The most valuable thing to me is we can make op
Hi @comaniac , Thanks for your suggestion! :)
Because of your suggestion and [Unified IR
Post](https://discuss.tvm.ai/t/ir-unified-tvm-ir-infra/4801), I think I need to
dig into the design and infrastructure of Relay for a while to see how to
design an DFA infrastructure that fits into both IRs.
@DKXXXL , thanks for the clarification and it seems fair enough to me :)
Then it seems like #4449, #3895 and this RFC should be unified and designed
together.
--
You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
https://github.c
Hi @comaniac , Thanks for commenting. :)
Yes. This is a real problem happening in the industrial context. The current
solution is either over-conservative or unsound.
About the name of "Data-flow Analysis", I think it is more a terminology
question. For example the CFA is also a kind of pr
Hey @DKXXXL, thanks for the example!
Just curious. Do you think the case of copy propagation caused dead code
happens in current workloads? Or this is more like a concern to the TVM
programming model as your example?
Another question is that the name "data-flow" analysis confuses me a bit,
bec
Hi @junrushao1994 ,
an over-simplified example from the industrial context is the following:
```python
...
B0 = tvm.compute((m,n), lambda i,j: A0[i,j] + 2*A1[i,j], name = "B0")
C0 = tvm.compute((m,n), lambda i,j: A0[i,j] + 2*A1[i,j], name = "C0")
D0 = tvm.compute((m,n), lambda i,j: B0[i,j] + 3*
Aah, the split of IR.
It seems like both side need their own analysis, and thus have to reinvent the
wheel twice.
Looking forward to the merge of IR.
--
You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
https://github.com/apache/
Hi @junrushao1994 , Thanks for the comments! :) I will get back to you about a
real world example as soon as possible.
But generally speaking, dead code elimination pass is required in some
workloads; and after TVM output program with intrinsics and not even targetting
CPU or GPU, LLVM or other
Hi,
Thank you for your detailed proposal! I think the design of data flow analysis
works for general cfgs.
However, I think I am not knowledgeable enough to understand the motivation and
use cases of liveness analysis in TVM IR. Could you kindly give a real-world
example how it may help analyz
### Comments: IsLattice
The basic usage is just:
```cpp
template
struct STD_SET_IS_LATTICE : public IsLattice> {
using SET = std::set;
public:
SET join(const SET& a, const SET& b);
SET meet(const SET& a, const SET& b);
const SET& top();
const SET& bottom();
bool equal
Hey, there is a similar RFC on the
topic(https://github.com/apache/incubator-tvm/issues/4449).
cc @gussmith23 @zhiics @jroesch @MarisaKirisame @icemelon9 @slyubomirsky
--
You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
https:
# Problem
When developing program passes on TVM IR (the one once was Halide IR), it is
normal to ask for all sorts of information requiring program analysis, for
example, live variable analysis for dead code elimination. This requirement
becomes urgent when TVM has to directly issue intrinsic a
25 matches
Mail list logo
