+1
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@areusch It's good to merge from my side
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> The main downside I see with this, is that all attributes are treated as
> strings since the type is hardcoded. However, I'm not sure if we can avoid
> this at all.
This could probably be solved by adding `type` and/or `default` arguments to
the argument parser, e.g.:
```
self._registe
> Im wondering whether should we provide an optional partitioning hook as well
> -- so then it can be anything (i.e. any Sequential) and let the default be a
> Sequential of MergeComposite, AnnotateTarget, MergeCompilerRegions,
> ParititionGraph. WDYT ?
Considering how partitioning is handled i
> One thing I'd like anwsered here what sort of control it will allow on the
> passes run there : MergeComposite, AnnotateTarget, MergeCompilerRegions and
> ParititionGraph.
So far we had planned to standardize on MergeComposite, AnnotateTarget,
MergeCompilerRegions and ParititionGraph. To get
[quote="manupa-arm, post:11, topic:12039"]
[quote="MJKlaiber, post:1, topic:12039"]
```
> class MyCustomAcceleratorPartitioner(UMAPartitioner):
@property
def target_name(self):
return "my_custom_accelerator"
def _register_patterns(self):
self._register_pattern("conv1d
@areusch Thanks for sharing the progress. I absolutely agree that P1 would be
the better solution. Is there a migration Path from your work to P1 or would
one need to implement it from scratch.
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Not sure whether it makes sense to revive such an old RFC, but has there been
any progress on a relay AOT? IMHO this would be very much needed, especially
for microcontrollers.
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