Re: [apache/tvm-rfcs] [RFC] Scalable vectors in TIR (PR #104)

> What I'm aiming at is to be able to lower the TIR to a generic CPU, that is > to an architecture that does not support SVE. The TIR will need to have some > default lowering in CodeGenLLVM/CodeGenCPU, so being able to do that is > important. For that, we should be able to assume that vscale is

Re: [apache/tvm] [CMSIS-NN] Move CMSIS_5 from SHA to release based upgrade (PR #15747)

Thanks @ashutosh-arm @NicolaLancellotti @leandron @neildhickey -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm/pull/15747#issuecomment-1752560774 You are receiving this because you are subscribed to this thread. Message ID:

Re: [apache/tvm] [CMSIS-NN] Move CMSIS_5 from SHA to release based upgrade (PR #15747)

Merged #15747 into main. -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm/pull/15747#event-10588194263 You are receiving this because you are subscribed to this thread. Message ID: