; Cc: dev@dpdk.org; nd
> Subject: Re: [dpdk-dev] Sync up status for Mellanox PMD barrier
> investigation
>
> Some update for this thread.
>
> In the most critical datapath of mlx5 PMD, there are some rte_cio_w/rmb,
> 'dmb osh' on aarch64, in use.
> C11 atomic is go
Some update for this thread.
In the most critical datapath of mlx5 PMD, there are some rte_cio_w/rmb, 'dmb
osh' on aarch64, in use.
C11 atomic is good for replacing the rte_smp_r/wmb to relax the data
synchronization barrier between CPUs.
However, mlx5 PMD needs to write data back to the HW, so
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