Hi Jerin
Thank you,
I mistakenly think x86 doen't need rte_smp_rmb().
Since rte_smp_rmb() only impact x86's compiler optimization, I will
simplify the codes as your suggestions
Cheers,
Jia
On 11/7/2017 5:57 PM, Jerin Jacob Wrote:
-Original Message-
Date: Tue, 7 Nov 2017 16:34:30
-Original Message-
> Date: Tue, 7 Nov 2017 16:34:30 +0800
> From: Jia He
> To: Jerin Jacob
> Cc: dev@dpdk.org, olivier.m...@6wind.com, konstantin.anan...@intel.com,
> bruce.richard...@intel.com, jianbo@arm.com, hemant.agra...@nxp.com,
> jie2@hxt-semitech.com, bing.z...@hxt-semit
On 11/7/2017 12:36 PM, Jerin Jacob Wrote:
-Original Message-
On option could be to change the prototype of update_tail() and make
compiler accommodate it for zero cost for arm64(Which I think, it it the
case. But you can check the generated instructions)
If not, move, __rte_ring_do_deq
-Original Message-
> Date: Mon, 6 Nov 2017 15:25:12 +0800
> From: Jia He
> To: Jerin Jacob
> Cc: dev@dpdk.org, olivier.m...@6wind.com, konstantin.anan...@intel.com,
> bruce.richard...@intel.com, jianbo@arm.com, hemant.agra...@nxp.com,
> jie2@hxt-semitech.com, bing.z...@hxt-semit
Hi Jerin
On 11/3/2017 8:56 PM, Jerin Jacob Wrote:
-Original Message-
[...]
g like that.
Ok, but how to distinguish following 2 options?
No clearly understood this question. For arm64 case, you can add
CONFIG_RTE_RING_USE_C11_MEM_MODEL=y in config/defconfig_arm64-armv8a-*
Sorry for
-Original Message-
> Date: Fri, 3 Nov 2017 09:46:40 +0800
> From: Jia He
> To: Jerin Jacob
> Cc: dev@dpdk.org, olivier.m...@6wind.com, konstantin.anan...@intel.com,
> bruce.richard...@intel.com, jianbo@arm.com, hemant.agra...@nxp.com,
> jie2@hxt-semitech.com, bing.z...@hxt-semit
Hi Jerin
On 11/3/2017 1:23 AM, Jerin Jacob Wrote:
-Original Message-
Date: Thu, 2 Nov 2017 08:43:30 +
From: Jia He
To: jerin.ja...@caviumnetworks.com, dev@dpdk.org, olivier.m...@6wind.com
Cc: konstantin.anan...@intel.com, bruce.richard...@intel.com,
jianbo@arm.com, hemant.a
-Original Message-
> Date: Thu, 2 Nov 2017 08:43:30 +
> From: Jia He
> To: jerin.ja...@caviumnetworks.com, dev@dpdk.org, olivier.m...@6wind.com
> Cc: konstantin.anan...@intel.com, bruce.richard...@intel.com,
> jianbo@arm.com, hemant.agra...@nxp.com, Jia He ,
> jie2@hxt-semit
-Original Message-
> Date: Thu, 2 Nov 2017 16:16:33 +
> From: "Ananyev, Konstantin"
> To: Jia He , "jerin.ja...@caviumnetworks.com"
> , "dev@dpdk.org" ,
> "olivier.m...@6wind.com"
> CC: "Richardson, Bruce" , "jianbo@arm.com"
> , "hemant.agra...@nxp.com" ,
> "jie2@hxt-semit
> -Original Message-
> From: Jia He [mailto:hejia...@gmail.com]
> Sent: Thursday, November 2, 2017 3:43 PM
> To: Ananyev, Konstantin ;
> jerin.ja...@caviumnetworks.com; dev@dpdk.org; olivier.m...@6wind.com
> Cc: Richardson, Bruce ; jianbo@arm.com;
> hemant.agra...@nxp.com; jie2@
Hi Ananyev
On 11/2/2017 9:26 PM, Ananyev, Konstantin Wrote:
Hi Jia,
-Original Message-
From: Jia He [mailto:hejia...@gmail.com]
Sent: Thursday, November 2, 2017 8:44 AM
To: jerin.ja...@caviumnetworks.com; dev@dpdk.org; olivier.m...@6wind.com
Cc: Ananyev, Konstantin ; Richardson, Bruce
Hi Jia,
> -Original Message-
> From: Jia He [mailto:hejia...@gmail.com]
> Sent: Thursday, November 2, 2017 8:44 AM
> To: jerin.ja...@caviumnetworks.com; dev@dpdk.org; olivier.m...@6wind.com
> Cc: Ananyev, Konstantin ; Richardson, Bruce
> ; jianbo@arm.com;
> hemant.agra...@nxp.com; Jia
We watched a rte panic of mbuf_autotest in our qualcomm arm64 server.
As for the possible race condition, please refer to [1].
Furthermore, there are 2 options as suggested by Jerin:
1. use rte_smp_rmb
2. use load_acquire/store_release(refer to [2]).
CONFIG_RTE_ATOMIC_ACQUIRE_RELEASE_BARRIER_PREFE
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