m Technology China) [mailto:gavin...@arm.com]
> > > > Sent: Monday, December 16, 2019 18:50
> > > > To: Li, Xiaoyun ; Wu, Jingjing
> > >
> > > > Cc: dev@dpdk.org; Maslekar, Omkar ;
> > > > sta...@dpdk.org; nd
> > > > Subject: RE: [dpdk
ilto:gavin...@arm.com]
> Sent: Monday, December 23, 2019 16:38
> To: Li, Xiaoyun ; Wu, Jingjing
> Cc: dev@dpdk.org; Maslekar, Omkar ;
> sta...@dpdk.org; nd ; jer...@marvell.com; Honnappa
> Nagarahalli ; Richardson, Bruce
> ; nd
> Subject: RE: [dpdk-dev] [PATCH v2] raw/ntb: fix
Hi Xiaoyun,
> -Original Message-
> From: Li, Xiaoyun
> Sent: Monday, December 23, 2019 3:52 PM
> To: Gavin Hu ; Wu, Jingjing
> Cc: dev@dpdk.org; Maslekar, Omkar ;
> sta...@dpdk.org; nd
> Subject: RE: [dpdk-dev] [PATCH v2] raw/ntb: fix write memory barrier issue
>
com; Xiaoyun Li
> > ; sta...@dpdk.org
> > Subject: [dpdk-dev] [PATCH v2] raw/ntb: fix write memory barrier issue
> >
> > All buffers and ring info should be written before tail register update.
> > This patch relocates the write memory barrier before updating tail
> > re
> -Original Message-
> From: Li, Xiaoyun
> Sent: Monday, December 16, 2019 9:59 AM
> To: Wu, Jingjing
> Cc: dev@dpdk.org; Maslekar, Omkar ; Li, Xiaoyun
> ; sta...@dpdk.org
> Subject: [PATCH v2] raw/ntb: fix write memory barrier issue
>
> All buffers and ring info should be written bef
> -Original Message-
> From: dev On Behalf Of Xiaoyun Li
> Sent: Monday, December 16, 2019 9:59 AM
> To: jingjing...@intel.com
> Cc: dev@dpdk.org; omkar.masle...@intel.com; Xiaoyun Li
> ; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH v2] raw/ntb: fix write memory b
All buffers and ring info should be written before tail register update.
This patch relocates the write memory barrier before updating tail register
to avoid potential issues.
Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions")
Cc: sta...@dpdk.org
Signed-off-by: Xiaoyun Li
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