On Wed, Oct 9, 2019 at 1:15 PM Jakub Grajciar -X (jgrajcia - PANTHEON
TECHNOLOGIES at Cisco) wrote:
>
>
>
> > -Original Message-
> > From: Phil Yang
> > Sent: Wednesday, October 9, 2019 4:05 AM
> > To: Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco)
> > ; ferruh.yi...@intel.
> -Original Message-
> From: Phil Yang
> Sent: Wednesday, October 9, 2019 4:05 AM
> To: Jakub Grajciar -X (jgrajcia - PANTHEON TECHNOLOGIES at Cisco)
> ; ferruh.yi...@intel.com; dev@dpdk.org
> Cc: tho...@monjalon.net; Damjan Marion (damarion)
> ; honnappa.nagaraha...@arm.com;
> gavin...
Using 'rte_mb' to synchronize the shared ring head/tail between producer
and consumer will stall the pipeline and damage performance on the weak
memory model platform such like AArch64. Meanwhile update the shared
ring head and tail are observable and ordered between CPUs on IA.
Optimized this ful
3 matches
Mail list logo
