Hi Honnappa,
> -Original Message-
> From: Honnappa Nagarahalli
> Sent: Thursday, August 29, 2019 6:49 AM
> To: Gavin Hu (Arm Technology China) ;
> dev@dpdk.org
> Cc: nd ; tho...@monjalon.net; jer...@marvell.com;
> pbhagavat...@marvell.com; qi.z.zh...@intel.com;
> bruce.richard...@intel.co
>
> As packet length extraction code was simplified,the ordering was not
> necessary any more.[1]
IMO, there is no relationship between the compiler barrier and [1] at least on
Arm platforms. I suggest we just say 'there is no reason for the compiler
barrier'.
I think this compiler barrier is no
As packet length extraction code was simplified,the ordering
was not necessary any more.[1]
2% performance gain was measured on Marvell ThunderX2.
4.3% performance gain was measure on Ampere eMAG80
[1] http://mails.dpdk.org/archives/dev/2016-April/037529.html
Fixes: ae0eb310f253 ("net/i40e: impl
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