gt;> Cc: Eads, Gage ; dev@dpdk.org;
> >> olivier.m...@6wind.com; arybche...@solarflare.com; Ananyev,
> >> Konstantin
> >> Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to
> >> pointer-width size
> >>
> >> On Fri, Jan 11, 201
] ring: change head and tail to pointer-width
size
On Fri, Jan 11, 2019 at 11:30:24AM +, Burakov, Anatoly wrote:
On 11-Jan-19 10:58 AM, Bruce Richardson wrote:
On Fri, Jan 11, 2019 at 10:40:19AM +, Burakov, Anatoly wrote:
<...>
+ * Copyright(c) 2016-2019 Intel Corpo
; Ananyev, Konstantin
>
> Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to
> pointer-width
> size
>
> On Fri, 11 Jan 2019 19:12:40 +
> "Eads, Gage" wrote:
>
> > > -Original Message-
> > > From: Burakov, Anatoly
> &g
hardson, Bruce
> > ; Ananyev, Konstantin
> >
> > Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to
> > pointer-width
> > size
> >
> > On 10-Jan-19 9:01 PM, Gage Eads wrote:
> > > For 64-bit architectures, doubling the head an
> -Original Message-
> From: Richardson, Bruce
> Sent: Friday, January 11, 2019 5:59 AM
> To: Burakov, Anatoly
> Cc: Eads, Gage ; dev@dpdk.org;
> olivier.m...@6wind.com; arybche...@solarflare.com; Ananyev, Konstantin
>
> Subject: Re: [dpdk-dev] [PATCH 1/6] ri
> -Original Message-
> From: Burakov, Anatoly
> Sent: Friday, January 11, 2019 4:25 AM
> To: Eads, Gage ; dev@dpdk.org
> Cc: olivier.m...@6wind.com; arybche...@solarflare.com; Richardson, Bruce
> ; Ananyev, Konstantin
>
> Subject: Re: [dpdk-dev] [PATCH 1/6] ring:
; Subject: Re: [dpdk-dev] [PATCH 1/6] ring: change head and tail to
> pointer-width
> size
>
> On Thu, 10 Jan 2019 15:01:17 -0600
> Gage Eads wrote:
>
> > For 64-bit architectures, doubling the head and tail index widths
> > greatly increases the time it takes fo
On 11-Jan-19 10:58 AM, Bruce Richardson wrote:
On Fri, Jan 11, 2019 at 10:40:19AM +, Burakov, Anatoly wrote:
<...>
+ * Copyright(c) 2016-2019 Intel Corporation
*/
/**
@@ -88,7 +88,7 @@ rte_event_ring_enqueue_burst(struct rte_event_ring *r,
const struct rte_event *eve
On Fri, Jan 11, 2019 at 10:40:19AM +, Burakov, Anatoly wrote:
> <...>
>
> > + * Copyright(c) 2016-2019 Intel Corporation
> >*/
> > /**
> > @@ -88,7 +88,7 @@ rte_event_ring_enqueue_burst(struct rte_event_ring *r,
> > const struct rte_event *events,
> > unsigned int
<...>
+ * Copyright(c) 2016-2019 Intel Corporation
*/
/**
@@ -88,7 +88,7 @@ rte_event_ring_enqueue_burst(struct rte_event_ring *r,
const struct rte_event *events,
unsigned int n, uint16_t *free_space)
{
- uint32_t prod_head, prod_next;
+ uin
On 10-Jan-19 9:01 PM, Gage Eads wrote:
For 64-bit architectures, doubling the head and tail index widths greatly
increases the time it takes for them to wrap-around (with current CPU
speeds, it won't happen within the author's lifetime). This is important in
avoiding the ABA problem -- in which a
On Thu, 10 Jan 2019 15:01:17 -0600
Gage Eads wrote:
> For 64-bit architectures, doubling the head and tail index widths greatly
> increases the time it takes for them to wrap-around (with current CPU
> speeds, it won't happen within the author's lifetime). This is important in
> avoiding the ABA
For 64-bit architectures, doubling the head and tail index widths greatly
increases the time it takes for them to wrap-around (with current CPU
speeds, it won't happen within the author's lifetime). This is important in
avoiding the ABA problem -- in which a thread mistakes reading the same
tail in
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