On Tue, Nov 28, 2017 at 06:13:35PM -0800, Ferruh Yigit wrote:
> On 11/23/2017 8:53 AM, Bruce Richardson wrote:
> > +ifeq ($(CC_AVX2_SUPPORT), 1)
> > + SRCS-$(CONFIG_RTE_LIBRTE_ACL) += i40e_rxtx_vec_avx2.c
>
> Minor issue:
> s/CONFIG_RTE_LIBRTE_ACL/CONFIG_RTE_LIBRTE_I40E_INC_VECTOR/
>
Ooops. Goo
On 11/23/2017 8:53 AM, Bruce Richardson wrote:
> +ifeq ($(CC_AVX2_SUPPORT), 1)
> + SRCS-$(CONFIG_RTE_LIBRTE_ACL) += i40e_rxtx_vec_avx2.c
Minor issue:
s/CONFIG_RTE_LIBRTE_ACL/CONFIG_RTE_LIBRTE_I40E_INC_VECTOR/
> +endif
Add a new Tx function using AVX2 instructions for higher performance. For
now, this functionality is limited to platforms with Intel Xeon Scalable
Processor(SP), Skylake uarch. The function to be used is selected at
runtime, not just at compile-time.
Signed-off-by: Bruce Richardson
---
drivers/
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