> >
> > Hi Jakub,
> > I am trying to review this patch. I am having difficulty in
> > understanding the implementation for the queue/ring, appreciate if you
> > could help me understand the logic.
>
> 'ring' refers to a ring buffer holding packet descriptors. These descriptors
> hold metadat
On 9/21/2020 1:21 PM, Jakub Grajciar -X (jgrajcia - PANTHEON TECH SRO at
Cisco) wrote:
Using 'rte_mb' to synchronize the shared ring head/tail between
producer and consumer will stall the pipeline and damage
performance on the weak memory model platforms, such like aarch64.
Relax the expensive
> > > >
> > > > Using 'rte_mb' to synchronize the shared ring head/tail between
> > > > producer and consumer will stall the pipeline and damage
> > > > performance on the weak memory model platforms, such like aarch64.
> > > >
> > > > Relax the expensive barrier with c11 atomic with explicit memor
Jakub Grajciar -X (jgrajcia - PANTHEON TECH SRO at Cisco) writes:
> > Subject: RE: [PATCH] net/memif: relax barrier for zero copy path
> >
> > Hi Jakub,
> > I am trying to review this patch. I am having difficulty in
> understanding
> > the implementation for the queue/ring, appreciate if yo
Hi Honnappa,
Inline comments...
> -Original Message-
> From: Honnappa Nagarahalli
> Sent: Saturday, September 19, 2020 12:49 AM
> To: Phil Yang ; Jakub Grajciar -X (jgrajcia - PANTHEON
> TECH SRO at Cisco) ; dev@dpdk.org
> Cc: Ruifeng Wang ; nd ; Honnappa
> Nagarahalli ; nd
> Subject: R
Hi Jakub,
I am trying to review this patch. I am having difficulty in
understanding the implementation for the queue/ring, appreciate if you could
help me understand the logic.
1) The S2M queues - are used to send packets from slave to master. My
understanding is that, the slave thread
On 9/11/2020 6:38 AM, Phil Yang wrote:
Using 'rte_mb' to synchronize the shared ring head/tail between producer
and consumer will stall the pipeline and damage performance on the weak
memory model platforms, such like aarch64.
Relax the expensive barrier with c11 atomic with explicit memory
orde
Using 'rte_mb' to synchronize the shared ring head/tail between producer
and consumer will stall the pipeline and damage performance on the weak
memory model platforms, such like aarch64.
Relax the expensive barrier with c11 atomic with explicit memory
ordering can improve 3.6% performance on thro
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